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ADS825EG4 bảng dữ liệu(PDF) 8 Page - Texas Instruments

tên linh kiện ADS825EG4
Giải thích chi tiết về linh kiện  ANALOG-TO-DIGITAL CONVERTERS
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ADS825EG4 bảng dữ liệu(HTML) 8 Page - Texas Instruments

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ADS822, ADS825
8
SBAS069B
APPLICATION INFORMATION
THEORY OF OPERATION
The ADS822 and ADS825 are high-speed CMOS ADCs
which employ a pipelined converter architecture consisting of
nine internal stages. Each stage feeds its data into the digital
error correction logic ensuring excellent differential linearity
and no missing codes at the 10-bit level. The output data
becomes valid on the rising clock edge (see Timing Dia-
gram). The pipeline architecture results in a data latency of
5 clock cycles.
The analog inputs of the ADS822 and ADS825 are differen-
tial track-and-hold, as shown in Figure 1. The differential
topology, along with tightly matched capacitors, produce a
high level of AC performance while sampling at very high rates.
FIGURE 1. Simplified Circuit of Input Track-and-Hold with
Timing Diagram.
The selection for the optimum interface configuration will
depend on the individual application requirements and sys-
tem structure. For example, communications applications
often process a band of frequencies that do not include DC,
whereas in imaging applications, the previously restored DC
level must be maintained correctly up to the ADC. Features
on the ADS822 and ADS825, such as the input range select
(RSEL pin) or the option for an external reference, provide
the needed flexibility to accommodate a wide range of
applications. In any case, the ADS822 and ADS825 should
be configured such that the application objectives are met
while observing the headroom requirements of the driving
amplifier in order to yield the best overall performance.
INPUT CONFIGURATIONS
AC-Coupled, Single-Supply Interface
See Figure 2 for the typical circuit for an AC-coupled analog
input configuration of the ADS822 and ADS825 while all
components are powered from a single +5V supply.
With the RSEL pin connected HI, the full-scale input range is
set to 2Vp-p. In this configuration, the top and bottom
references (REFT, REFB) provide an output voltage of +3.5V
and +1.5V, respectively. Two resistors ( 2x 1.62k
Ω) are used
to create a common-mode voltage (VCM) of approximately
+2.5V to bias the inputs of the driving amplifier A1. Using the
OPA680 on a single +5V supply, its ideal common-mode
point is at +2.5V which coincides with the recommended
common-mode input level for the ADS822 and ADS825. This
obviates the need of a coupling capacitor between the
amplifier and the converter. Even though the OPA680 has an
AC gain of +2, the DC gain is only +1 due to the blocking
capacitor at resistor RG.
The addition of a small series resistor (RS) between the
output of the op amp and the input of the ADS822 and
ADS825 will be beneficial in almost all interface configura-
tions. This will decouple the op amp’s output from the
capacitive load and avoid gain peaking, which can result in
increased noise. For best spurious and distortion perfor-
mance, the resistor value should be kept below 100
Ω.
Furthermore, the series resistor in combination with the 10pF
capacitor establishes a passive low-pass filter limiting the
bandwidth for the wideband noise, thus helping improve the
SNR performance.
AC-Coupled, Dual Supply Interface
The circuit provided in Figure 3 illustrates typical connections
for the analog input in case the selected amplifier operates
on dual supplies. This might be necessary to take full
advantage of very low distortion operational amplifiers, like
the OPA642. The advantage is that the driving amplifier can
be operated with a ground-referenced bipolar signal swing.
This will keep the distortion performance at its lowest, since
the signal range stays within the linear region of the op amp
and sufficient headroom to the supply rails can be main-
tained. By capacitively coupling the single-ended signal to
the input of the ADS822 and ADS825, its common-mode
requirements can easily be satisfied with two resistors con-
nected between the top and bottom references.
The ADS822 and ADS825 allow their analog inputs to be
driven either single-ended or differentially. The typical con-
figuration for the ADS822 and ADS825 is the single-ended
mode in which the input track-and-hold performs a single-
ended-to-differential conversion of the analog input signal.
Both inputs (IN, IN) require external biasing using a com-
mon-mode voltage that is typically at the mid-supply level
(+VS/2).
The following application discussion focuses on the single-
ended configuration. Typically, its implementation is easier to
achieve and the rated specifications for the ADS822 and
ADS825 are characterized using the single-ended mode of
operation.
DRIVING THE ANALOG INPUT
The ADS822 and ADS825 achieve excellent AC performance
either in the single-ended or differential mode of operation.
φ1
φ1
φ2
φ1
φ1
φ1
φ1
φ1
φ2
φ1
φ2
φ1
φ2
IN
IN
OUT
OUT
Op Amp
Bias
V
CM
Op Amp
Bias
V
CM
C
H
C
I
C
I
C
H
Input Clock (50%)
Internal Non-overlapping Clock


Số phần tương tự - ADS825EG4

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Mô tả tương tự - ADS825EG4

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