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ADS830 bảng dữ liệu(PDF) 7 Page - Texas Instruments |
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ADS830 bảng dữ liệu(HTML) 7 Page - Texas Instruments |
7 / 16 page ADS830 7 SBAS086A APPLICATION INFORMATION THEORY OF OPERATION The ADS830 is a high-speed CMOS A/D converter which employs a pipelined converter architecture consisting of 6 internal stages. Each stage feeds its data into the digital error correction logic ensuring excellent differential linearity and no missing codes at the 8-bit level. The output data becomes valid on the rising clock edge (see Timing Diagram). The pipeline architecture results in a data latency of 4 clock cycles. The analog input of the ADS830 is a differential track and hold, see Figure 1. The differential topology along with tightly matched capacitors produce a high level of ac perfor- mance while sampling at very high rates. The ADS830 allows its analog inputs to be driven either single-ended or differentially. The typical configuration for the ADS830 is for the single-ended mode in which the input track and hold performs a single-ended to differential con- version of the analog input signal. Both inputs (IN, IN) require external biasing using a com- mon-mode voltage that is typically at the mid-supply level (+VS/2). The following application discussion focuses on the single- ended configuration. Typically, its implementation is easier to achieve and the rated specifications for the ADS830 are characterized using the single-ended mode of operation. DRIVING THE ANALOG INPUT The ADS830 achieves excellent ac performance either in the single-ended or differential mode of operation. The selection for the optimum interface configuration will depend on the individual application requirements and system structure. For example, communications applications often process a band of frequencies that does not include DC, whereas in imaging applications, the previously restored DC level must be maintained correctly up to the A/D converter. Features on the ADS830 like the input range select (RSEL pin) or the option for an external reference provide the needed flexibil- ity to accommodate a wide range of applications. In any case, the ADS830 should be configured such that the appli- cation objectives are met while observing the headroom requirements of the driving amplifier in order to yield the best overall performance. INPUT CONFIGURATIONS AC-Coupled, Single-Supply Interface Figure 2 shows the typical circuit for an ac-coupled analog input configuration of the ADS830 where all components are powered from a single +5V supply. With the RSEL pin connected HIGH, the full-scale input range is set to 2Vp-p. In this configuration, the top and bottom references (REFT, REFB) provide an output voltage of +3.0V and +2.0V, respectively. Two resistors ( 2 x 1k Ω) are used to create a common-mode voltage (VCM) of ap- proximately +2.5V to bias the inputs of the driving ampli- fier. Using the OPA681 on a single +5V supply, its ideal common-mode point is at +2.5V. This coincides with the recommended common-mode input level for the ADS830 thus, obviating the need for a coupling capacitor between the amplifier and the converter. Even though the OPA681 has an ac gain of +2, the dc gain is only +1 due to the blocking capacitor at resistor RG. The addition of a small series resistor (RS) between the output of the op amp and the input of the ADS830 will be beneficial in almost all interface configurations. This will de-couple the op amp’s output from the capacitive load and avoid gain peaking, which can result in increased noise. For best spurious and distortion performance, the resistor value should be kept below 75 Ω. The series resistor in combina- tion with the 47pF capacitor establishes a passive low-pass filter, limiting the bandwidth for the wideband noise thus help improving the SNR performance. AC-Coupled, Dual Supply Interface The circuit provided in Figure 3 shows typical connections for the analog input in case the selected amplifier operates on dual supplies. This might be necessary to take full advantage of very low distortion operational amplifiers, such as the OPA642. The advantage is that the driving amplifier can be operated with a ground referenced bipolar signal swing. This will keep the distortion performance at its lowest since the signal range stays within the linear region of the op amp and sufficient headroom to the supply rails can be maintained. By capacitively coupling the single-ended signal to the input of the ADS830, its common-mode re- quirements can easily be satisfied with two resistors con- nected between the top and bottom reference. φ1 φ1 φ2 φ1 φ1 φ1 φ1 φ1 φ2 φ1 φ2 φ1 φ2 IN IN OUT OUT Op Amp Bias V CM Op Amp Bias V CM C H C I C I C H Input Clock (50%) Internal Non-overlapping Clock FIGURE 1. Simplified Circuit of Input Track and Hold with Timing Diagram. |
Số phần tương tự - ADS830 |
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Mô tả tương tự - ADS830 |
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