ADS1130IPWR datasheet(7/17 Pages) TI1

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AbruptChangeinExternalV

IN

V

IN

DRDY/DOUT

Startof

Conversion

FirstConversion;

includes

unsettledV .

IN

SecondConversion;

V

settled,but

digitalfilter

unsettled.

IN

ThirdConversion;

V

settled,but

digitalfilter

unsettled.

IN

FourthConversion;

V

settled,but

digitalfilter

unsettled.

IN

FifthConversion;

V

anddigital

filterboth

settled.

IN

Conversion

Time

ADS1130

www.ti.com

SBAS458A – JUNE 2009 – REVISED SEPTEMBER 2012

Table 2. Ideal Output Code vs Input Signal(1)

SETTLING TIME

INPUT SIGNAL VIN

Large changes in the input signal require settling

(AINP – AINN)

IDEAL OUTPUT

time. For example, an external multiplexer in front of

≥ +0.5VREF/64

1FFFFh

the ADS1130 can cause large changes in the input

00001h

(+0.5VREF/64)/(2

17 – 1)

voltage

when

switching

the

multiplexer

input

0

00000h

channels. Abrupt changes in the input require four

data conversion cycles to settle. When continuously

3FFFFh

(–0.5VREF/64)/(2

17 – 1)

converting, five readings may be necessary in order

≤ –0.5VREF/64

40000h

to settle the data. If the change in input occurs in the

(1) Excludes effects of noise, INL, offset, and gain errors.

middle

of

the

first

conversion,

four

more

full

conversions of the fully-settled input are required to

DATA READY/DATA OUTPUT (DRDY/DOUT)

get fully-settled data. Discard the first four readings

because they contain only partially-settled data.

This digital output pin serves two purposes. First, it

Figure 5 illustrates the settling time for the ADS1130

indicates when new data are ready by going low.

in Continuous Conversion mode.

Afterwards, on the first rising edge of SCLK, the

DRDY/DOUT

changes

function

and

begins

DATA RATE

outputting the conversion data, most significant bit

(MSB) first. Data are shifted out on each subsequent

The ADS1130 data rate is set by the SPEED pin, as

SCLK rising edge. After all 18 bits have been

shown in Table 1. When SPEED is low, the data rate

retrieved, the pin can be forced high with additional

is nominally 10SPS. This data rate provides the

SCLKs. It then stays high until new data are ready.

lowest noise, and also has excellent rejection of both

This configuration is useful when polling on the status

50Hz

and

60Hz

line-cycle

interference.

For

of DRDY/DOUT to determine when to begin data

applications requiring fast data rates, setting SPEED

retrieval.

high selects a data rate of nominally 80SPS.

SERIAL CLOCK INPUT (SCLK)

Table 1. Data Rate Settings

This digital input shifts serial data out with each rising

SPEED PIN

DATA RATE

edge. This input has built-in hysteresis, but care

0

10SPS

should still be taken to ensure a clean signal. Glitches

1

80SPS

or slow-rising signals can cause unwanted additional

shifting. For this reason, it is best to make sure the

DATA FORMAT

rise and fall times of SCLK are both less than 50ns.

The ADS1130 outputs 18 bits of data in binary two’s

complement format. The least significant bit (LSB)

has a weight of (0.5VREF/64)(2

17 – 1). The positive

full-scale input produces an output code of 1FFFFh

and the negative full-scale input produces an output

code of 40000h. The output clips at these codes for

signals exceeding full-scale. Table 2 summarizes the

ideal output codes for different input signals.

Figure 5. Settling Time in Continuous Conversion Mode

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