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ADS5270IPFPT bảng dữ liệu(PDF) 7 Page - Texas Instruments

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tên linh kiện ADS5270IPFPT
Giải thích chi tiết về linh kiện  8-Channel, 12-Bit, 40MSPS Analog-to-Digital Converter
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Trang chủ  http://www.ti.com
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ADS5270IPFPT bảng dữ liệu(HTML) 7 Page - Texas Instruments

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LVDS DIGITAL DATA AND CLOCK OUTPUTS
SWITCHING CHARACTERISTICS
ADS5270
www.ti.com............................................................................................................................................... SBAS293F – JANUARY 2004 – REVISED JANUARY 2009
Test conditions at IO = 3.5mA, RLOAD = 100Ω, and CLOAD = 6pF. IO refers to the current setting for the LVDS buffer. RLOAD is the differential
load resistance between the LVDS pair. CLOAD is the effective single-ended load capacitance between each of the LVDS pins and ground.
CLOAD includes the receiver input parasitics as well as the routing parasitics. Measurements are done with a 1-inch transmission line of 100Ω
characteristic impedance between the device and the load. All LVDS specifications are characterized, but not parametrically tested at
production. LCLKOUT refers to (LCLKP – LCLKN); ADCLKOUT refers to (ADCLKP – ADCLKN); DATA OUT refers to (OUTP – OUTN); and
ADCLK refers to the input sampling clock.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DC SPECIFICATIONS(1)
VOH Output Voltage High, OUTP or OUTN
RLOAD = 100Ω ± 1%; See LVDS Timing Diagram, Page 8
1265
1365
1465
mV
VOL Output Voltage Low, OUTP or OUTN
RLOAD = 100Ω ± 1%
940
1040
1140
mV
|VOD| Output Differential Voltage
RLOAD = 100Ω ± 1%
275
325
375
mV
VOS Output Offset Voltage
(2)
RLOAD = 100Ω ± 1%; See LVDS Timing Diagram, Page 8
1.1
1.2
1.3
V
RO Output Impedance, Differential
Normal Operation
13
k
RO Output Impedance, Differential
Power-Down
20
k
CO Output Capacitance
(3)
4
pF
|
ΔVOD| Change in |VOD| Between 0 and 1
RLOAD = 100Ω ± 1%
10
mV
ΔVOS Change Between 0 and 1
RLOAD = 100Ω ± 1%
25
mV
ISOUT Output Short-Circuit Current
Drivers Shorted to Ground
40
mA
ISOUTNP Output Current
Drivers Shorted Together
12
mA
DRIVER AC SPECIFICATIONS
ADCLKOUT Clock Duty Cycle(4)
45
50
55
%
LCLKOUT Duty Cycle(4)
44
50
56
%
Data Setup Time(5)(6)
0.7
ns
Data Hold Time(6)(7)
0.61
ns
LVDS Outputs Rise/Fall Time(8)
IO = 2.5mA
400
ps
IO = 3.5mA
180
300
500
ps
IO = 4.5mA
230
ps
IO = 6.0mA
180
ps
LCLKOUT Rising Edge to ADCLKOUT Rising Edge(9)
0.74
1.04
1.34
ns
ADCLKOUT Rising Edge to LCLKOUT Falling Edge(9)
0.74
1.04
1.34
ns
ADCLKOUT Rising Edge to DATA OUT Transition(9)
–0.35
0
+0.35
ns
(1)
The dc specifications refer to the condition where the LVDS outputs are not switching, but are permanently at a valid logic level 0 or 1.
(2)
VOS refers to the common-mode of OUTP and OUTN.
(3)
Output capacitance inside the device, from either OUTP or OUTN to ground.
(4)
Measured between zero crossings.
(5)
DATA OUT (OUTP – OUTN) crossing zero to LCLKOUT (LCLKP – LCLKN) crossing zero.
(6)
Data setup and hold time accounts for data-dependent skews, channel-to-channel mismatches, as well as effects of clock jitter within
the device.
(7)
LCLKOUT crossing zero to DATA OUT crossing zero.
(8)
Measured from –100mV to +100mV on the differential output for rise time, and +100mV to –100mV for fall time.
(9)
Measured between zero crossings.
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = maximum specified, 50% clock duty cycle,
AVDD = 3.3V, LVDD = 3.3V, –1dBFS, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SWITCHING SPECIFICATIONS
tSAMPLE
25
50
ns
tD(A) Aperture Delay
2
4
6.5
ns
Aperture Jitter (uncertainty)
1
ps rms
tD(pipeline) Latency
6.5
Cycles
tPROP Propagation Delay
3
4.8
6.5
ns
Copyright © 2004–2009, Texas Instruments Incorporated
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