SCLK

CS

SCLK

Z3

Z2

Z1

Z0

DB10

DONT

DONTC ADD2

ADD1

ADD0

DONTC DONTC DONTC

DB11

DB9

DB8

DB1

16

8

7

6

5

4

3

2

1

DB0

DIN

DOUT

SCLK

CS

ADC124S021

www.ti.com

SNAS277F – MARCH 2005 – REVISED MARCH 2013

Figure 4. ADC124S021 Serial Timing Diagram

Figure 5. SCLK and CS Timing Parameters

Specification Definitions

ACQUISITION TIME is the time required to acquire the input voltage. That is, it is time required for the hold

capacitor to charge up to the input voltage.

APERTURE DELAY is the time between the fourth falling SCLK edge of a conversion and the time when the

input signal is acquired or held for conversion.

CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input

voltage to a digital word.

CROSSTALK is the coupling of energy from one channel into the other channel, or the amount of signal energy

from one analog input that appears at the measured analog input.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1

LSB.

DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The

specification here refers to the SCLK

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise

and Distortion or SINAD. ENOB is defined as (SINAD

− 1.76) / 6.02 and says that the converter is

equivalent to a perfect ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental

drops 3 dB below its low frequency value for a full scale input.

FULL SCALE ERROR (FSE) is a measure of how far the last code transition is from the ideal 1½ LSB below

+

where

•

•

FSE can be expressed in Volts, LSB or percent of full scale range

(1)

Copyright © 2005–2013, Texas Instruments Incorporated

Submit Documentation Feedback

7

Product Folder Links: ADC124S021