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ADS5203IPFBR bảng dữ liệu(PDF) 11 Page - Texas Instruments

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ADS5203
SBAS258A – JUNE 2002 – REVISED JULY 2002
www.ti.com
11
PRINCIPLE OF OPERATION
The ADS5203 implements a dual high-speed, 10-bit,
40MSPS converter in a cost-effective CMOS process.
The differential inputs on each channel are sampled
simultaneously. Signal inputs are differential and the
clock signal is single-ended. The clock signal is either
80MHz
or
40MHz,
depending
on
the
device
configuration set by the user. Powered from 3.3V, the
dual-pipeline design architecture ensures low-power
operation and 10-bit resolution. The digital inputs are
3.3V
TTL/CMOS
compatible.
Internal
voltage
references are included for both bottom and top
voltages. Alternatively, the user may apply externally
generated reference voltages. In doing so, the input
range can be modified to suit the application.
The ADC is a 5-stage pipelined ADC with 4 stages of
fully-differential switched capacitor sub-ADC/MDAC
pairs and a single sub-ADC in stage 5. All stages deliver
2 bits of the final conversion result. A digital error
correction
is
used
to
compensate
for
modest
comparator offsets in the sub-ADCs.
SAMPLE-AND-HOLD AMPLIFIER
Figure 5 shows the internal SHA architecture. The
circuit is balanced and fully differential for good supply
noise rejection. The sampling circuit has been kept as
simple as possible to obtain good performance for
high-frequency input signals.
Figure 5. SHA Architecture.
The analog input signal is sampled on capacitors CSP
and CSN while the internal device clock is low. The
sampled voltage is transferred to capacitors CHP and
CHN and held on these while the internal device clock
is high. The SHA can sample both single-ended and
differential input signals.
The load presented to the AIN pin consists of the
switched input sampling capacitor CS (approximately
2pF) and its various stray capacitances. A simplified
equivalent circuit for the switched capacitor input is
shown in Figure 6. The switched capacitor circuit is
modeled as a resistor RIN. fCLK is the clock frequency,
which is 40MHz at full speed, and CS is the sampling
capacitor. Using 25
Ω series resistors and a differential
15pF capacitor at the A/B+ and A/B– inputs is
recommended to reduce noise.
NOTE: AIN can be any variation
of A or B inputs.
VCM = 0.5 S (V(A/B+) + V(A/B–))
VCM
fCLK = 40MHz
Figure 6. Equivalent Circuit for the Switched
Capacitor Input.
ANALOG INPUT, DIFFERENTIAL
CONNECTION
The analog input of the ADS5203 is a differential
architecture that can be configured in various ways
depending on the signal source and the required level
of performance. A fully differential connection will
deliver the best performance from the converter. The
analog inputs must not go below AVSS or above AVDD.
The inputs can be biased with any common-mode
voltage provided that the minimum and maximum input
voltages stay within the range AVSS to AVDD. It is
recommended to bias the inputs with a common-mode
voltage around AVDD/2. This can be accomplished
easily with the output voltage source CML, which is
equal to AVDD/2. CML is made available to the user to
help simplify circuit design. This output voltage source
is not designed to be a reference or to be loaded but
makes an excellent DC bias source and stays well
within the analog input common-mode voltage range
over temperature.
Not Recommended For New Designs


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