 |
công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
|
công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
ADS5122 bảng dữ liệu(PDF) 4 Page - Texas Instruments |
|
||||||||||||||||||||||||||||||
ADS5122 bảng dữ liệu(HTML) 4 Page - Texas Instruments |
|
|
4 / 21 page  ADS5122 4 SBAS272E www.ti.com ADS5122 AC CHARACTERISTICS AVDD = DVDD = 1.8V, DRVDD = 3.3V, 50% Clock Duty Cycle, CLK = 65MSPS, Analog Input at –0.5dBFS Input Span, Internal Voltage Reference, TMIN = −40°C, TMAX = +85°C, and typical values at TA = 25°C, unless otherwise noted. ADS5122 SWITCHING CHARACTERISTICS AVDD = DVDD = 1.8V, DRVDD = 3.3V, 50% Clock Duty Cycle, CLK = 65MSPS, Analog Input at –0.5dBFS Input Span, Internal Voltage Reference, TMIN = −40°C, and TMAX = +85°C. Typical values at TA = 25°C, unless otherwise noted. PARAMETER CONDITION MIN TYP MAX UNITS Maximum Conversion Rate 5 65 MSPS Clock Duty Cycle DCASEL Enabled 30 to 70 % Data Latency(1) 6.5 Clk Cycles Clock ↓ to Data Valid tDO(1) 810 ns OE ↓ to Outputs Enabled tEN(1) 8ns OE ↑ Rising to Outputs Tri-Stated tDIS 8ns Aperture Delay 1ns Aperture Uncertainty (Jitter) 2 ps, r ms PARAMETER CONDITION MIN TYP MAX UNITS Signal-to-Noise Ratio (SNR) fIN = 3.5MHz 56 59 dB fIN = 10MHz 56 59 dB fIN = 20MHz 59 dB Signal-to-Noise and Distortion (SINAD) fIN = 3.5MHz 56 58 dB fIN = 10MHz 56 58 dB fIN = 20MHz 58 dB Effective Number of Bits (ENOB) fIN = 3.5MHz 9.0 9.3 Bits fIN = 10MHz 9.0 9.3 Bits fIN = 20MHz 9.3 Bits Spurious-Free Dynamic Range (SFDR) fIN = 3.5MHz 65 72 dBc fIN = 10MHz 65 72 dBc fIN = 20MHz 68 dBc 2nd-Harmonic Distortion (HD2) fIN = 3.5MHz 68 83 dBc fIN = 10MHz 68 79 dBc fIN = 20MHz 79 dBc 3rd-Harmonic Distortion (HD3) fIN = 3.5MHz 65 72 dBc fIN = 10MHz 65 72 dBc fIN = 20MHz 68 dBc 2-Tone Intermodulation Distortion (IMD) f1 = 4.43MHz, f2 = 4.53MHz at –6.5dB –69 dBFS Channel-to-Channel Crosstalk fIN = 10MHz, DRVDD = 3.3V 89 dB Effective Resolution Bandwidth 30 MHz Over-Voltage Recovery Time(1) 20 ns Differential Gain(1) ±1% Differential Phase(1) ±0.25 Degrees NOTE: (1) Assured by design. TIMING DIAGRAM (Per ADC Channel) Analog Input CLK OE D[9:0] S – 5 S – 6S – 4S – 3S – 2S – 1S1 S2 S3 t DO t DIS t EN Sample 1 Sample 2 89 7 6 5 4 3 2 1 |
Số phần tương tự - ADS5122 |
|
Mô tả tương tự - ADS5122 |
|
|
|
Link URL |
| Chính sách bảo mật |
| ALLDATASHEET.VN |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Vietnamese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
