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ADS5120CZHK bảng dữ liệu(PDF) 10 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  8-Channel, 10-Bit, 40MSPS, 1.8V CMOS ANALOG-TO-DIGITAL CONVERTER
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Trang chủ  http://www.ti.com
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ADS5120
10
SBAS247E
www.ti.com
APPLICATION INFORMATION
CONVERTER OPERATION
The ADS5120 is an 8-channel, simultaneous sampling ADC.
Its low power (100mW/channel) and high sampling rate of
40MSPS is achieved using a state-of-the-art switched ca-
pacitor pipeline architecture built on an advanced low-volt-
age CMOS process. The ADS5120 primarily operates from a
+1.8V single supply. For additional interfacing flexibility, the
digital I/O supply (DRVDD) can be set to either +1.8V or
+3.3V. The ADC core of each channel consists of 10 pipeline
stages. Each of the 10 stages produces one digital bit per
stage. Both the rising and the falling clock edges are utilized
to propagate the sample through the pipeline every half
clock, for a total of five clock cycles. Two additional clock
cycles are needed to pass the sample data through the
digital error correction logic and the output latches. The total
pipeline delay, or data latency, is therefore seven clock
cycles long. Since a common clock controls the timing of all
eight channels, the analog signal is sampled at the same
time, as well as the data on the parallel ports which becomes
updated simultaneously.
ANALOG INPUTS
The analog input for each channel of the ADS5120 consists
of a differential track-and-hold amplifier implemented using a
switched capacitor technique, shown in Figure 1. This differ-
ential input topology along with closely matched capacitors
produces a high level of AC performance up to high sampling
rates.
slew current to charge and discharge the input sampling
capacitor while the track-and-hold amplifier is in track mode.
The input impedance of the ADS5120 is also a function of the
sampling rate. As the sampling frequency increases, the
input impedance decreases linearly at a rate of 1/fs. For most
applications, this does not represent a limitation since the
impedance remains relatively high, for example, approxi-
mately 83k
Ω at the max sampling rate of 40MSPS. For
applications using an op amp to drive the ADC, it is recom-
mended that a series resistor, typically 10
Ω to 50Ω, be added
between the amplifier output and the converter inputs. This
will isolate the converter capacitive input from the driver and
avoid potential gain peaking, or instability.
INPUT BIASING
The ADS5120 operates from a single +1.8V analog supply,
and requires each of the analog inputs (AIN+, AIN–) to be
externally biased by a suitable common-mode voltage. For
example, with a common-mode voltage of +1V, the 1VPP full-
scale, differential input signal will swing symmetrically around
+1V, or between 0.75V and 1.25V. This is determined by the
two reference voltages, the top reference (REFT), and the
bottom reference (REFB). Typically, the input common-mode
level is related to the reference voltages and defined as
(REFT + REFB)/2. This reference mid-point is provided at the
CML pin and can directly be used for input biasing purposes.
The voltage at CML will assume the mid-point for either
internal or external reference operation. In any case, it is
recommended to bypass the CML pin with a ceramic 0.1
µF
capacitor.
DRIVING THE ANALOG INPUTS
Differential versus Single-Ended
The analog input of the ADS5120 allows it to be driven either
single-ended or differentially. Differential operation of the
ADS5120 requires an input signal that consists of an in-
phase and a 180
° out-of-phase part simultaneously applied
to the inputs (AIN+, AIN–). The full-scale input range of the
ADS5120 is defined by the reference voltages according to
FSR = 2 x (REFT – REFB). For a typical 1VPP range, the
differential input configuration only requires each input to see
a signal swing of 0.5VPP. Operating the converter in single-
ended configuration requires the full 1VPP swing applied to
the chosen input. The differential operation offers a number
of advantages, which in most applications will be instrumen-
tal in achieving the best dynamic performance of the ADS5120:
• The signal swing is half of that required for the single-
ended operation and is therefore less demanding to achieve
while maintaining good linearity performance from the
signal source.
• The reduced signal swing allows for more headroom of the
interface circuitry and therefore a wider selection of the
best suitable driver op amp.
• Even-order harmonics are minimized.
• Improves the noise immunity based on the converter’s
common-mode input rejection.
T&H
C
IN
V
BIAS
V
BIAS
C
IN
S
1
S
2
S
3
S
4
S
6
S
5
AIN+
AIN–
Tracking Phase: S
1, S2, S3, S4 closed; S5, S6 open.
Hold Phase:
S
1, S2, S3, S4 open; S5, S6 closed.
ADS5120
FIGURE 1. Simplified Circuit of Input Track-and-Hold.
INPUT IMPEDANCE
Because of the switched capacitor input track-and-hold am-
plifier, the input impedance of the ADS5120 is effectively
capacitive, and the driving source needs to provide sufficient


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