công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
ADC12DL080 bảng dữ liệu(PDF) 10 Page - Texas Instruments |
|
ADC12DL080 bảng dữ liệu(HTML) 10 Page - Texas Instruments |
10 / 34 page ADC12DL080 SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com DC and Logic Electrical Characteristics (1)(2)(3) (continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 80 MHz, fIN = 40 MHz, CL = 10 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C Units Parameter Test Conditions Typical(4) Limits(4) (Limits) POWER SUPPLY CHARACTERISTICS PD Pin = DGND, VREF = VA 112.5 136 mA (max) IA Analog Supply Current PD Pin = VD 15 mA PD Pin = DGND 23 26 mA (max) ID Digital Supply Current PD Pin = VD , fCLK = 0 0 mA PD Pin = DGND, CL = 10 pF (5) 15 mA IDR Digital Output Supply Current PD Pin = VD, fCLK = 0 0 mA PD Pin = DGND, CL = 10 pF (6) 447 535 mW (max) Total Power Consumption PD Pin = VD 50 mW Rejection of Full-Scale Error with PSRR Power Supply Rejection Ratio 80 dB VA = 3.0V vs. 3.6V (5) IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0 x f0 + C1 x f1 +....C11 x f11) where VDR is the output driver power supply voltage, Cn is total capacitance on the output pin, and fn is the average frequency at which that pin is toggling. (6) Excludes IDR. See Note 5. AC Electrical Characteristics (1) (2) (3) (4) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, External VREF = +1.0V, fCLK = 80 MHz, fIN = 40 MHz, CL = 10 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C Units Parameter Test Conditions Typical(5) Limits(5) (Limits) fCLK1 Maximum Clock Frequency 80 MHz (min) fCLK2 Minimum Clock Frequency 10 MHz tCH Clock High Time Duty Cycle Stabilizer On 6.25 3.75 ns (min) tCL Clock Low Time Duty Cycle Stabilizer On 6.25 3.75 ns (min) tCH Clock High Time Duty Cycle Stabilizer Off 6.25 5 ns (min) tCL Clock Low Time Duty Cycle Stabilizer Off 6.25 5 ns (min) tr, tf Clock Rise and Fall Times 2 ns (max) tCONV Conversion Latency 7 Clock Cycles 3.5 ns (min) Data Output Delay after Rising Clock tOD 7.5 Edge 11 ns (max) Output Set up time from data output tOSU See(6) 7.2 4 ns (min) transition to rising edge of DRDY Output Hold time from rising edge of tOH See(6) 5.3 4 ns (min) DRDY to next data output transition tAD Aperture Delay 2 ns tAJ Aperture Jitter 0.3 ps rms tDIS Data outputs into Hi-Z Mode 10 ns tEN Data Outputs Active after Hi-Z Mode 10 ns (1) The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per Note 4 of the Absolute Maximum Ratings Table. However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100 mV. As an example, if VA is +3.3V, the full-scale input voltage must be ≤+3.4V to ensure accurate conversions. See Figure 2. (2) To ensure accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin. (3) With the test condition for VREF = +1.0V (2VP-P differential input), the 12-bit LSB is 488 µV. (4) Timing specifications are tested at TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge. (5) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are to AOQL (Average Outgoing Quality Level). (6) This parameter is ensured by design and/or characterization and is not tested in production. 10 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC12DL080 |
Số phần tương tự - ADC12DL080_15 |
|
Mô tả tương tự - ADC12DL080_15 |
|
|
Link URL |
Chính sách bảo mật |
ALLDATASHEET.VN |
Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |