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AD9951 bảng dữ liệu(PDF) 5 Page - Analog Devices |
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AD9951 bảng dữ liệu(HTML) 5 Page - Analog Devices |
5 / 28 page AD9951 Rev. 0 | Page 5 of 28 Parameter Temp Min Typ Max Unit TIMING CHARACTERISTICS Serial Control Bus Maximum Frequency FULL 25 Mbps Minimum Clock Pulse Width Low FULL 7 ns Minimum Clock Pulse Width High FULL 7 ns Maximum Clock Rise/Fall Time FULL 2 ns Minimum Data Setup Time DVDD_I/O = 3.3 V FULL 3 ns Minimum Data Setup Time DVDD_I/O = 1.8 V FULL 5 ns Minimum Data Hold Time FULL 0 ns Maximum Data Valid Time FULL 25 ns Wake-Up Time2 FULL 1 ms Minimum Reset Pulse Width High FULL 5 SYSCLK Cycles3 I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.3 V FULL 4 ns I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.3 V FULL 6 ns I/O UPDATE, SYNC_CLK Hold Time FULL 0 ns Latency I/O UPDATE to Frequency Change Prop Delay 25°C 24 SYSCLK Cycles I/O UPDATE to Phase Offset Change Prop Delay 25°C 24 SYSCLK Cycles I/O UPDATE to Amplitude Change Prop Delay 25°C 16 SYSCLK Cycles CMOS LOGIC INPUTS Logic 1 Voltage @ DVDD_I/O (Pin 43) = 1.8 V 25°C 1.25 V Logic 0 Voltage @ DVDD_I/O (Pin 43) = 1.8 V 25°C 0.6 V Logic 1 Voltage @ DVDD_I/O (Pin 43) = 3.3 V 25°C 2.2 V Logic 0 Voltage @ DVDD_I/O (Pin 43) = 3.3 V 25°C 0.8 V Logic 1 Current 25°C 3 12 µA Logic 0 Current 25°C 12 µA Input Capacitance 25°C 2 pF CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 1.8 V Logic 1 Voltage 25°C 1.35 V Logic 0 Voltage 25°C 0.4 V CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 3.3 V Logic 1 Voltage 25°C 2.8 V Logic 0 Voltage 25°C 0.4 V POWER CONSUMPTION (AVDD = DVDD = 1.8 V) Single-Tone Mode 25°C 162 171 mW Rapid Power-Down Mode 25°C 150 160 mW Full-Sleep Mode 25°C 20 27 mW SYNCHRONIZATION FUNCTION4 Maximum SYNC Clock Rate (DVDD_I/O = 1.8 V) 25°C 62.5 MHz Maximum SYNC Clock Rate (DVDD_I/O = 3.3 V) 25°C 100 MHz SYNC_CLK Alignment Resolution5 25°C ±1 SYSCLK Cycles 1 To achieve the best possible phase noise, the largest amplitude clock possible should be used. Reducing the clock input amplitude will reduce the phase noise per- formance of the device. 2 Wake-up time refers to the recovery from analog power-down modes (see the section). The longest time required is for the reference clock multiplier PLL to relock to the reference. The wake-up time assumes there is no capacitor on DACBP and that the recommended PLL loop filter values are used. Power-Down Functions of the AD9951 3 SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency, the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier is not used, the SYSCLK fre- quency is the same as the external reference clock frequency. 4 SYNC_CLK = ¼ SYSCLK rate. For SYNC_CLK rates ≥ 50 MHz, the high speed sync enable bit, CFR2<11>, should be set. 5 This parameter indicates that the digital synchronization feature cannot overcome phase delays (timing skew) between system clock rising edges. If the system clock edges are aligned, the synchronization function should not increase the skew between the two edges. |
Số phần tương tự - AD9951 |
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Mô tả tương tự - AD9951 |
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