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DAC0830LCM bảng dữ liệu(PDF) 5 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
tên linh kiện DAC0830LCM
Giải thích chi tiết về linh kiện  8-Bit P Compatible, Double-Buffered D to A Converters
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nhà sản xuất  NSC [National Semiconductor (TI)]
Trang chủ  http://www.national.com
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DAC0830LCM bảng dữ liệu(HTML) 5 Page - National Semiconductor (TI)

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Electrical Characteristics
V
REF=10.000 VDC unless otherwise noted. Boldface limits apply over temperature, TMIN≤TA≤TMAX. For all other limits
T
A=25˚C.
Symbol
Parameter
Conditions
See
Note
V
CC=15.75 VDC
V
CC=12
V
DC±5% to 15
V
DC ±5%
V
CC=4.75 VDC
V
CC=5
V
DC±5%
Limit
Units
Typ
(Note 12)
Tested
Limit
(Note 5)
Design Limit
(Note 6)
Typ
(Note 12)
Tested
Limit
(Note 5)
Design
Limit
(Note 6)
AC CHARACTERISTICS
t
s
Current Setting
V
IL=0V,
V
IH=5V
1.0
1.0
µs
Time
t
W
Write and XFER
V
IL=0V,
V
IH=5V
11
100
250
375
600
Pulse Width Min
9
320
320
900
900
t
DS
Data Setup Time
V
IL=0V,
V
IH=5V
9
100
250
375
600
Min
320
320
900
900
t
DH
Data Hold Time
V
IL=0V,
V
IH=5V
9
30
50
ns
Min
30
50
t
CS
Control Setup
Time
V
IL=0V,
V
IH=5V
9
110
250
600
900
Min
320
320
1100
1100
t
CH
Control Hold Time V
IL=0V,
V
IH=5V
90
0
10
0
0
Min
00
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is PD =(TJMAX −TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device,
TJMAX = 125˚C (plastic) or 150˚C (ceramic), and the typical junction-to-ambient thermal resistance of the J package when board mounted is 80˚C/W. For the N
package, this number increases to 100˚C/W and for the V package this number is 120˚C/W.
Note 4: For current switching applications, both IOUT1 and IOUT2 must go to ground or the “Virtual Ground” of an operational amplifier. The linearity error is degraded
by approximately VOS ÷VREF. For example, if VREF = 10V thena1mVoffset, VOS,onIOUT1 or IOUT2 will introduce an additional 0.01% linearity error.
Note 5: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 6: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels.
Note 7: Guaranteed at VREF=±10 VDC and VREF=±1VDC.
Note 8: The unit “FSR” stands for “Full Scale Range.” “Linearity Error” and “Power Supply Rejection” specs are based on this unit to eliminate dependence on a
particular VREF value and to indicate the true performance of the part. The “Linearity Error” specification of the DAC0830 is “0.05% of FSR (MAX)”. This guarantees
that after performing a zero and full scale adjustment (see Sections 2.5 and 2.6), the plot of the 256 analog voltage outputs will each be within 0.05%xVREF of a
straight line which passes through zero and full scale.
Note 9: Boldface tested limits apply to the LJ and LCJ suffix parts only.
Note 10: A 100nA leakage current with Rfb=20k and VREF=10V corresponds to a zero error of (100x10
−9x20x103)x100/10 which is 0.02% of FS.
Note 11: The entire write pulse must occur within the valid data interval for the specified tW,tDS,tDH, and tS to apply.
Note 12: Typicals are at 25˚C and represent most likely parametric norm.
Note 13: Human body model, 100 pF discharged through a 1.5 k
Ω resistor.
www.national.com
5


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