March 1988

10

Philips Semiconductors

HCMOS family characteristics

FAMILY SPECIFICATIONS

HC TYPES

AC waveforms 74HC

AC waveforms 74HC

Fig.3 Input rise and fall times, transition times and propagation delays for combinatorial logic ICs.

handbook, halfpage

MGK564

10%

90%

90%

50%

50%

INPUT

OUTPUT

tr

tf

tPHL

tTHL

tPLH

tTLH

10%

GND

VCC

handbook, full pagewidth

MGK569

10 %

90%

50%

CLOCK

INPUT

VCC

GND

50%

DATA

INPUT

VCC

GND

10%

90%

50%

OUTPUT

tsu

tPHL

tPLH

tsu

tTLH

tTHL

50%

SET,

RESET,

PRESET

INPUT

VCC

GND

tr

tf

tWH

th

th

tWL

trem

1/fmax

Fig.4

Set-up times, hold times, removal times, propagation delays and the maximum clock pulse frequency for

sequential logic ICs.

(1) In Fig.4 the active transition of the clock is going from LOW-to-HIGH and the active level of the forcing signals (SET, RESET

and PRESET) is HIGH. The actual direction of the transition of the clock input and the actual active levels of the forcing signals

are specified in the individual device data sheet.