LM98722 datasheet(9/150 Pages) TI1

tên linh kiện	LM98722

Giải thích chi tiết về linh kiện	Channel, 16-Bit, 45 MSPS Analog Front End

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LM98722

www.ti.com

SNAS487B – SEPTEMBER 2009 – REVISED MARCH 2015

Electrical Characteristics (continued)

The following specifications apply for VA = VD = VC = 3.3 V, CL = 10 pF, and fINCLK = 15 MHz unless otherwise specified. All

other limits TA = 25°C.

PARAMETER

TEST CONDITIONS

MIN(1)

TYP(2) MAX(1)(3)

UNIT

INPUT SAMPLING CIRCUIT SPECIFICATIONS

CDS Gain=1x, PGA Gain=1x

2.3

VIN

Input Voltage Level

Vp-p

CDS Gain=2x, PGA Gain= 1x

1.22

Source Followers Off

19

CDS Gain = 1x

(-103)

25

μA

(-95)

OSX = VA (OSX = AGND)

Source Followers Off

Sample and Hold Mode Input

33

IIN_SH

CDS Gain = 2x

(-152)

50

μA

Leakage Current

(-141)

OSX = VA (OSX = AGND)

Source Followers On

20

CDS Gain = 2x

(-250)

250

nA

(-50)

OSX = VA (OSX = AGND)

Sample/Hold Mode

CDS Gain = 1x

2.5

pF

CSH

Equivalent Input Capacitance

CDS Gain = 2x

4

pF

CDS Mode

Source Followers Off

10

IIN_CDS

(-250)

250

nA

OSX = VA (OSX = AGND)

(-50)

Input Leakage Current

CLPIN Switch Resistance (OSX

RCLPIN

16

55

Ω

to VCLP Node)

VCLP REFERENCE CIRCUIT SPECIFICATIONS

VCLP Voltage 000

VCLP Voltage Setting = 000

0.85VA

V

VCLP Voltage 001

VCLP Voltage Setting = 001

0.9VA

V

VCLP Voltage 010

VCLP Voltage Setting = 010

0.95VA

V

VCLP Voltage 011

VCLP Voltage Setting = 011

0.6VA

V

VVCLP

VCLP Voltage 100

VCLP Voltage Setting = 100

0.55VA

V

VCLP Voltage 101

VCLP Voltage Setting = 101

0.4VA

V

VCLP Voltage 110

VCLP Voltage Setting = 110

0.35VA

V

VCLP Voltage 111

VCLP Voltage Setting = 111

0.15VA

V

VCLP DAC Short Circuit Output

ISC

30

mA

Current

BLACK LEVEL OFFSET DAC SPECIFICATIONS

Resolution

10

Bits

Monotonicity

Ensured by characterization

CDS Gain = 1x

Minimum DAC Code = 0x000

-614

mV

Maximum DAC Code = 0x3FF

614

Offset Adjustment Range

Referred to AFE Input

CDS Gain = 2x

Minimum DAC Code = 0x000

-307

mV

Maximum DAC Code = 0x3FF

307

Minimum DAC Code = 0x000

-17500

-16130

Offset Adjustment Range

LSB

Referred to AFE Output

Maximum DAC Code = 0x3FF

+16130

+17500

CDS Gain = 1x

mV

1.2

DAC LSB Step Size

(32)

Referred to AFE Output

(LSB)

DNL

Differential Non-Linearity

-0.85 +0.74/ -0.37

+2.4

LSB

INL

Integral Non-Linearity

-2.5 +0.72/ -0.56

+2.5

LSB

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nhà sản xuất	tên linh kiện	bảng dữ liệu	Giải thích chi tiết về linh kiện
National Semiconductor ...	LM98722	481Kb / 14P	3 Channel, 16-Bit, 45 MSPS Analog Front End with LVDS/CMOS Output, Integrated CCD/CIS Sensor Timing Generator and Spread Spectrum Clock Generation
Texas Instruments	LM98722	708Kb / 20P	[Old version datasheet] 3 Channel, 16-Bit, 45 MSPS Analog Front End with LVDS/CMOS Output Integrated CCD/CIS Sensor Timing Generator and Spread Spectrum Clock Generation
	LM98722CCMT	708Kb / 20P	[Old version datasheet] 3 Channel, 16-Bit, 45 MSPS Analog Front End with LVDS/CMOS Output Integrated CCD/CIS Sensor Timing Generator and Spread Spectrum Clock Generation
	LM98722CCMTX	708Kb / 20P	[Old version datasheet] 3 Channel, 16-Bit, 45 MSPS Analog Front End with LVDS/CMOS Output Integrated CCD/CIS Sensor Timing Generator and Spread Spectrum Clock Generation
	LM98722	708Kb / 20P	[Old version datasheet] 3 Channel, 16-Bit, 45 MSPS Analog Front End with LVDS/CMOS Output Integrated CCD/CIS Sensor Timing Generator and Spread Spectrum Clock Generation

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Mô tả tương tự - LM98722

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