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LM98725CCMT bảng dữ liệu(PDF) 7 Page - Texas Instruments |
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LM98725CCMT bảng dữ liệu(HTML) 7 Page - Texas Instruments |
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7 / 145 page  LM98725 www.ti.com SNAS474H – APRIL 2009 – REVISED MARCH 2015 6.4 Electrical Characteristics The following specifications apply for VA = VD = VR = VC = 3.3 V, CL = 10 pF, and fINCLK = 27 MHz unless otherwise specified. all other limits TA = 25°C. (1) PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT CMOS DIGITAL INPUT DC SPECIFICATIONS (RESETb, SH_R, SCLK, SENb) VIH Logical “1” Input Voltage 2.0 V VIL Logical “0” Input Voltage 0.8 V VIHYST Logic Input Hysteresis 0.6 V VIH = VD: RESET, SEN 100 nA IIH Logical “1” Input Current SH_R, SCLK, SDI, CAL 65 μA CE 30 VIL = DGND: RESET, SEN –65 μA IIL Logical “0” Input Current SH_R, SCLK, SDI, CAL –100 nA CE –30 μA CMOS DIGITAL OUTPUT DC SPECIFICATIONS (SH1 to SH5, RS, CP, PHIA, PHIB, PHIC) VOH Logical “1” Output Voltage IOUT = -0.5 mA 3.0 V VOL Logical “0” Output Voltage IOUT = 1.6 mA 0.21 V IOS Output Short Circuit Current VOUT = DGND 18 mA VOUT= VD –25 IOZ CMOS Output TRI-STATE VOUT = DGND 20 nA Current VOUT = VD –25 CMOS DIGITAL OUTPUT DC SPECIFICATIONS (CMOS DATA OUTPUTS) VOH Logical “1” Output Voltage IOUT = -0.5 mA 2.3 V VOL Logical “0” Output Voltage IOUT = 1.6 mA 0.12 V IOS Output Short Circuit Current VOUT = DGND 12 mA VOUT= VD –14 IOZ CMOS Output TRI-STATE VOUT = DGND 20 nA Current VOUT = VD –25 LVDS/CMOS CLOCK RECEIVER DC SPECIFICATIONS (INCLK+ and INCLK-PINS) VIHL Differential LVDS Clock 200 mV High Threshold Voltage RL = 100 Ω VCM (LVDS Input Common Mode Voltage)= 1.25 V VILL Differential LVDS Clock –200 mV Low Threshold Voltage VIHC CMOS Clock 2.0 V High Threshold Voltage INCLK- = DGND VILC CMOS Clock 0.8 V Low Threshold Voltage IIHL CMOS Clock 230 260 μA Input High Current IILC CMOS Clock –135 –120 μA Input Low Current (1) The analog inputs are protected as shown in Figure 2. Input voltage magnitudes beyond the supply rails will not damage the device, provided the current is limited per Note 4 under the Absolute Maximum Ratings Table. However, input errors will be generated If the input goes above VA and below AGND. (2) Test limits are specified to Texas Instruments' AOQL (Average Outgoing Quality Level). (3) Typical figures are at TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical specifications are not ensured. Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LM98725 |
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