LM98722CCMT datasheet(4/150 Pages) TI1

tên linh kiện	LM98722CCMT

Giải thích chi tiết về linh kiện	Channel, 16-Bit, 45 MSPS Analog Front End

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nhà sản xuất	TI1 [Texas Instruments]

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LM98722

SNAS487B – SEPTEMBER 2009 – REVISED MARCH 2015

www.ti.com

Pin Descriptions(1)

I/O

TYP

RES

DESCRIPTION

NO.

NAME

1

PHIC2

O

D

PU

Configurable high speed sensor timing output.

2

PHIC1

O

D

PD

Configurable high speed sensor timing output.

3

SH1

O

D

PU

Configurable low speed sensor timing output.

Chip Serial Interface Address Setting Input

CE LEVEL

ADDRESS

4

CE

I

D

VD

01

Float

10

DGND

00

5

CAL

I

D

PD

Initiate calibration sequence. Leave unconnected or tie to DGND if unused.

6

RESET

I

D

PU

Active-low master reset. NC when function not being used.

7

SH_R

I

D

PD

External request for an SH interval.

8

SDI

I

D

PD

Serial Interface Data Input.

9

SDO

O

D

Serial Interface Data Output.

10

SCLK

I

D

PD

Serial Interface shift register clock.

11

SEN

I

D

PU

Active-low chip enable for the Serial Interface.

12

VA

P

Analog power supply. Bypass voltage source with 4.7

μF and pin with 0.1μF to AGND.

13

AGND

P

Analog ground return.

14

VA

P

Analog power supply. Bypass voltage source with 4.7

μF and pin with 0.1μF to AGND.

15

VREFB

O

A

Bottom of ADC reference. Bypass with a 0.1

μF capacitor to ground.

16

VREFT

O

A

Top of ADC reference. Bypass with a 0.1

μF capacitor to ground.

17

VA

P

Analog power supply. Bypass voltage source with 4.7

μF and pin with 0.1μF to AGND.

18

AGND

P

Analog ground return.

Input Clamp Voltage. Normally bypassed with a 0.1

μF , and a 4.7μF capacitor to

19

VCLP

IO

A

AGND. An external reference voltage may be applied to this pin.

20

VA

P

Analog power supply. Bypass voltage source with 4.7

μF and pin with 0.1μF to AGND.

21

IBIAS

O

A

Bias setting pin. Connect a 9.0 k

Ω 1% resistor to AGND.

22

AGND

P

Analog ground return.

23

OSR

I

A

Analog input signal. Typically sensor Red output AC-coupled thru a capacitor.

24

AGND

P

Analog ground return.

25

OSG

I

A

Analog input signal. Typically sensor Green output AC-coupled thru a capacitor.

26

AGND

P

Analog ground return.

27

OSB

I

A

Analog input signal. Typically sensor Blue output AC-coupled thru a capacitor.

Charge Pump Filter Capacitor. Bypass this supply pin with a 0.1

μF capacitor to

28

CPOFILT2

A

CPOFILT1.

29

DGND

P

Digital ground return.

Charge Pump Filter Capacitor. Bypass this supply pin with a 0.1

μF capacitor to

30

CPOFILT1

A

CPOFILT2.

31

DVB

O

D

Digital Core Voltage bypass. Not an input. Bypass with 0.1

μF capacitor to DGND.

Clock Input. Non-Inverting input for LVDS clocks or CMOS clock input. CMOS clock is

32

INCLK+

I

D

selected when pin 33 is held at DGND, otherwise clock is configured for LVDS

operation.

33

INCLK-

I

D

Clock Input. Inverting input for LVDS clocks, connect to DGND for CMOS clock.

DOUT7/

Bit 7 of the digital video output bus in CMOS Mode, LVDS Frame Clock+ in LVDS

34

O

D

Mode.

TXCLK+

DOUT6/

Bit 6 of the digital video output bus in CMOS Mode, LVDS Frame Clock- in LVDS

35

O

D

Mode.

TXCLK-

(1)

(I=Input), (O=Output), (IO=Bi-directional), (P=Power), (D=Digital), (A=Analog), (PU=Pull Up with an internal resistor), (PD=Pull Down

with an internal resistor.).

4

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