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ADS42JB69IRGCT bảng dữ liệu(PDF) 1 Page - Texas Instruments |
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ADS42JB69IRGCT bảng dữ liệu(HTML) 1 Page - Texas Instruments |
1 / 76 page Product Folder Sample & Buy Technical Documents Tools & Software Support & Community ADS42JB49, ADS42JB69 SLAS900F – OCTOBER 2012 – REVISED DECEMBER 2014 ADS42JBx9 Dual-Channel, 14- and 16-Bit, 250-MSPS Analog-to-Digital Converters 1 Features 2 Applications 1 • Dual-Channel ADCs • Communication and Cable Infrastructure • 14- and 16-Bit Resolution • Multi-Carrier, Multimode Cellular Receivers • Maximum Clock Rate: 250 MSPS • Radar and Smart Antenna Arrays • JESD204B Serial Interface • Broadband Wireless • Test and Measurement Systems – Subclass 0, 1, 2 Compliant • Software-Defined and Diversity Radios – Up to 3.125 Gbps • Microwave and Dual-Channel I/Q Receivers – Two and Four Lanes Support • Repeaters • Analog Input Buffer with High-Impedance Input • Power Amplifier Linearization • Flexible Input Clock Buffer: Divide-by-1, -2, and -4 3 Description • Differential Full-Scale Input: 2 VPP and 2.5 VPP The ADS42JB69 and ADS42JB49 are high-linearity, (Register Programmable) dual-channel, 16- and 14-bit, 250-MSPS, analog-to- • Package: 9-mm × 9-mm VQFN-64 digital converters (ADCs). These devices support the • Power Dissipation: 850 mW/Ch JESD204B serial interface with data rates up to 3.125 Gbps. The buffered analog input provides • Aperture Jitter: 85 fS rms uniform input impedance across a wide frequency • Internal Dither range while minimizing sample-and-hold glitch energy • Channel Isolation: 100 dB making it easy to drive analog inputs up to very high • Performance: input frequencies. A sampling clock divider allows more flexibility for system clock architecture design. – fIN = 170 MHz at 2 VPP, –1 dBFS The devices employ internal dither algorithms to – SNR: 73.3 dBFS provide excellent spurious-free dynamic range – SFDR: 93 dBc for HD2, HD3 (SFDR) over a large input frequency range. – SFDR: 100 dBc for Non HD2, HD3 Device Information(1) – fIN = 170 MHz at 2.5 VPP, –1 dBFS PART NUMBER PACKAGE INTERFACE OPTION – SNR: 74.7 dBFS 14-bit DDR or QDR LVDS ADS42JB49 VQFN (64) – SFDR: 89 dBc for HD2, HD3 and 14-bit JESD204B 95 dBc for Non HD2, HD3 16-bit DDR or QDR LVDS ADS42JB69 VQFN (64) 16-bit JESD204B (1) For all available packages, see the orderable addendum at the end of the datasheet. space space 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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