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ADS1220IPW bảng dữ liệu(PDF) 6 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  Low-Power, Low-Noise, 24-Bit, ADC for Small-Signal Sensors
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ADS1220IPW bảng dữ liệu(HTML) 6 Page - Texas Instruments

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ADS1220
SBAS501B – MAY 2013 – REVISED FEBRUARY 2015
www.ti.com
6.5 Electrical Characteristics
Minimum and maximum specifications apply from TA = –40°C to +125°C. Typical specifications are at TA = 25°C.
All specifications are at AVDD = 3.3 V, AVSS = 0 V, DVDD = 3.3 V, PGA enabled, DR = 20 SPS, and external Vref = 2.5 V
(unless otherwise noted).
(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Absolute input current
See the Typical Characteristics
Differential input current
See the Typical Characteristics
SYSTEM PERFORMANCE
Resolution (no missing codes)
24
Bits
Normal mode
20, 45, 90, 175, 330, 600, 1000
SPS
DR
Data rate
Duty-cycle mode
5, 11.25, 22.5, 44, 82.5, 150, 250
SPS
Turbo mode
40, 90, 180, 350, 660, 1200, 2000
SPS
Noise (input-referred)
See the Noise Performance section
INL
Integral nonlinearity
Gain = 1 to 128, VCM = 0.5 AVDD, best fit
(2)
-15
±6
15
ppmFSR
PGA disabled, gain = 1 to 4, differential inputs
±4
µV
VIO
Input offset voltage
Gain = 1, differential inputs, TA = 25°C
–30
±4
30
µV
Gain = 2 to 128, differential inputs
±4
µV
PGA disabled, gain = 1 to 4
0.25
µV/°C
Offset drift
Gain = 1 to 128, TA = –40°C to +85°C
(2)
0.08
0.3
µV/°C
Gain = 1 to 128
0.25
µV/°C
Offset match
Match between any two inputs
±20
µV
PGA disabled, gain = 1 to 4
±0.015%
Gain error
Gain = 1 to 128, TA = 25°C
–0.1%
±0.015%
0.1%
PGA disabled, gain = 1 to 4
1
ppm/°C
Gain drift
Gain = 1 to 128(2)
1
4
ppm/°C
50 Hz ±3%, DR = 20 SPS, external CLK,
105
dB
50/60 bit = 10
60 Hz ±3%, DR = 20 SPS, external CLK,
NMRR
Normal-mode rejection ratio(2)
105
dB
50/60 bit = 11
50 Hz or 60 Hz ±3%, DR = 20 SPS,
90
dB
external CLK, 50/60 bit = 01
At dc, gain = 1
90
105
dB
CMRR
Common-mode rejection ratio
f(CM) = 50 Hz, DR = 2000 SPS
(2)
95
115
dB
f(CM) = 60 Hz, DR = 2000 SPS
(2)
95
115
dB
AVDD at dc, VCM = 0.5 AVDD, gain = 1
80
105
dB
PSRR
Power-supply rejection ratio
DVDD at dc, VCM = 0.5 AVDD, gain = 1
(2)
100
115
dB
INTERNAL VOLTAGE REFERENCE
Initial accuracy
TA = 25°C
2.045
2.048
2.051
V
Reference drift(2)
5
30
ppm/°C
Long-term drift
1000 hours
110
ppm
VOLTAGE REFERENCE INPUTS
Reference input current
REFP0 = Vref, REFN0 = AVSS
±10
nA
INTERNAL OSCILLATOR
Internal oscillator accuracy
Normal mode
–2%
±1%
2%
(1)
PGA disabled means the low-noise PGA is powered down and bypassed. Gains of 1, 2, and 4 are still possible in this case.
See the Bypassing the PGA section for more information.
(2)
Minimum and maximum values are ensured by design and characterization data.
6
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