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ADCV08832CIMX bảng dữ liệu(PDF) 10 Page - National Semiconductor (TI) |
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10 / 14 page Functional Description (Continued) 5. During the conversion, the output of the SAR compara- tor indicates whether the successive analog input is greater than (high) or less than (low) a series of voltages generated internally from a ratioed capacitor array (first 5 bits) and a resistor ladder (last 3 bits). After each comparison, the output of the comparator is clocked to DO on the falling edge of CLK. 6. After 8 clock periods the successive approximation rou- tine is completed. 7. Next, the stored data in the successive approximation register is loaded into an internal shift register and shifted out LSB first. The DO line then goes low until CS is returned high. 8. The DI and DO lines may be tied together and controlled through a bi-directional processor I/O bit with one wire. This is possible because the DI input is valid only during the MUX addressing interval, while the DO line is still in a high impedance state. 3.0 Reducing Power Consumption At 3.3V supply, the ADCV08832 consumes about 330 µA when CS is logic low. When CS is pulled high the device will enter a low power mode to minimize total power consump- tion. In low power mode some analog circuitry and digital logic are put in a static, low power condition. Also, DO, the output driver is taken into a TRI-STATE mode. To optimize static power consumption, special attention must be given to the digital input logic signals: CLK, CS, DI. Each digital input has a large CMOS buffer between V CC and GND. A traditional TTL level high (2.4V) will be sufficient for each input to read a logical “1”. However, there could be a large V IH to VCC voltage difference at each input. Such a voltage difference would cause excessive static power dis- sipation, even when CS is high and the part is low power mode. Therefore, to minimize the static power dissipation, it is recommended that all digital logic levels should equal the converter’s supply. Various CMOS logic is particularly well suited for this application. 4.0 THE ANALOG INPUTS The most important feature of the ADCV08832 is that it can be located right at the analog signal source and through just a few wires can communicate with a controlling processor. This in itself greatly minimizes circuitry to maintain analog signal accuracy which otherwise is most susceptible to noise pickup. However, the following must be considered for situ- ations in which the analog input sources are noisy or riding on a large common-mode voltage. In a true differential input stage, any signal that is common to both “+” and “-” inputs is cancelled. For the ADCV08832 the positive input of a selected channel pair is only sampled once before the start of a conversion during the acquisition time (t ca). The negative input needs to be stable during the complete conversion sequence because it is sampled before every decision in the SAR sequence. Therefore, any AC common-mode signal present on the analog inputs will not be completely cancelled and will cause some conversion errors. The linear worse case approximation of a common mode sinusoidal signal error is: V error(MAX) = VPEAK (2πfCM)(tconv) Where f CM is the frequency of the common-mode signal, V PEAK is its peak voltage value, and tconv is the A/D’s con- version time (t conv = 13/fCLK). For a 60 Hz common-mode signal to generate a 1⁄4 LSB error (5 mV) with the converter running at 500 kHz, its peak value would have to be 0.328V. 4.1 Sample and Hold The ADCV08832 provides a built-in sample-and-hold to ac- quire the input signal. The sample and hold can sample input signals in either single-ended or pseudo differential mode. 4.2 Input Op Amps When driving the analog inputs with an op amp it is important that the op amp settle within the allowed time. To achieve the full sampling rate, the analog input should be driven with a low impedance source (100 Ω) or a high-speed op amp such as the LM6142. Higher impedance sources or slower op amps can easily be accommodated by allowing more time for the analog input to settle. 4.3 Source Resistance The analog inputs of the ADCV08832 appears as a 13 pF capacitor (C IN) in series with a 300Ω resistor (RON). CIN gets switched between the selected “+” and “-” inputs during each conversion cycle. Large external source resistors will slow the settling of the inputs. It is important that the overall RC time constants be short enough to allow the analog input to completely settle. 4.4 Board Layout Considerations, Grounding and Bypassing The ADCV08832 should be used with an analog ground plane and single-point grounding techniques. The GND pin should be tied directly to the ground plane. The supply pin should be bypassed to the ground plane with a ceramic capacitor with leads as short as possible in single ended mode. All analog inputs should be referenced directly to the single-point ground. 5.0 OPTIONAL ADJUSTMENTS 5.1 Zero Error The offset of the A/D does not require adjustment. If the minimum analog input voltage value, V IN(MIN), is not ground a zero offset can be done. In differential mode the converter can be made to output 0000 0000 digital code for this minimum input voltage by biasing any V IN(−) input at this V IN(MIN) value. The zero error of the A/D converter relates to the location of the first riser of the transfer function and can be measured by grounding the V IN(−) input and applying a small magnitude positive voltage to the V IN(+) input. Zero error is the differ- ence between the actual DC input voltage which is neces- sary to just cause an output digital code transition from 0000 0000 to 0000 0001 and the ideal 1⁄2 LSB value (1⁄2 LSB = 6.4 mV). 6.0 DYNAMIC PERFORMANCE Dynamic performance specifications are often useful in ap- plications requiring waveform sampling and digitization. Typically, a memory buffer is used to capture a stream of consecutive digital outputs for post processing. Capturing a number of samples that is a power of 2 (ie, 1024, 2048, 4096) allows the Fast Fourier Transform (FFT) to be used to www.national.com 10 |
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