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ADC12441883 bảng dữ liệu(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
tên linh kiện ADC12441883
Giải thích chi tiết về linh kiện  Dynamically-Tested Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold
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Digital and DC Electrical Characteristics
The following specifications apply for DVCC e AVCC ea50V Vb eb50V VREF ea50V and fCLK e 20 MHz unless
otherwise specified Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C
(Notes 6 and 7) (Continued)
Symbol
Parameter
Conditions
Typical
Limit
Units
(Note 9)
(Notes 10 19)
(Limits)
IOUT
TRI-STATE Output Leakage
VOUT e 0V
b
001
b
3
m
A (max)
Current
VOUT e 5V
001
3
m
A (max)
ISOURCE
Output Source Current
VOUT e 0V
b
20
b
60
mA (min)
ISINK
Output Sink Current
VOUT e 5V
20
80
mA (min)
DICC
DVCC Supply Current
fCLK e 2 MHz CS e ‘‘1’’
1
2
mA (max)
AICC
AVCC Supply Current
fCLK e 2 MHz CS e ‘‘1’’
28
6
mA (max)
Ib
Vb Supply Current
fCLK e 2 MHz CS e ‘‘1’’
28
6
mA (max)
AC Electrical Characteristics
The following specifications apply for DVCC e AVCC ea50V Vb eb50V tr e tf e 20 ns unless otherwise specified
Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C (Notes 6 and 7)
Symbol
Parameter
Conditions
Typical
Limit
Units
(Note 9)
(Notes 10 19)
(Limits)
fCLK
Clock Frequency
05
MHz (min)
40
20
MHz (max)
Clock Duty Cycle
50
%
40
% (min)
60
% (max)
tC
Conversion Time
27(1fCLK)
27(1fCLK) a 300 ns
(max)
fCLKe 20 MHz
135
m
s
tA
Acquisition Time
RSOURCE e 50X
7(1fCLK)
7(1fCLK) a 300 ns
(max)
(Note 15)
fCLK e 20 MHz
35
m
s
tZ
Auto Zero Time
26(1fCLK)
26(1fCLK)
(max)
fCLK e 20 MHz
13
m
s
tCAL
Calibration Time
1396(1fCLK)
max
fCLK e 20 MHz
698
706
m
s (max)
tW(CAL)L
Calibration Pulse Width
(Note 16)
60
200
ns (min)
tW(WR)L
Minimum WR Pulse Width
60
200
ns (min)
tACC
Maximum Access Time
CL e 100 pF
(Delay from Falling Edge of
50
85
ns (max)
RD to Output Data Valid)
t0H t1H
TRI-STATE Control
RL e 1kX
(Delay from Rising Edge of
CL e 100 pF
30
90
ns (max)
RD to Hi-Z State)
tPD(INT)
Maximum Delay from Falling Edge of
100
175
ns (max)
RD or WR to Reset of INT
Note 1
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is
functional but do not guarantee specific performance limits For guaranteed specifications and test conditions see the Electrical Characteristics The guaranteed
specifications apply only for the test conditions listed Some performance characteristics may degrade when the device is not operated under the listed test
conditions
Note 2
All voltages are measured with respect to AGND and DGND unless otherwise specified
Note 3
When the input voltage (VIN) at any pin exceeds the power supply rails (VIN k Vb or VIN l (AVCC or DVCC) the current at that pin should be limited to
5 mA The 20 mA maximum package input current rating allows the voltage at any four pins with an input current limit of 5 mA to simultaneously exceed the power
supply voltages
4


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