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ADC12451 bảng dữ liệu(PDF) 5 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
tên linh kiện ADC12451
Giải thích chi tiết về linh kiện  Dynamically-Tested Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold
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ADC12451 bảng dữ liệu(HTML) 5 Page - National Semiconductor (TI)

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AC Electrical Characteristics (Continued)
The following specifications apply for DVCC e AVCC ea50V Vb eb50V tr e tf e 20 ns unless otherwise specified
Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C (Notes 6 and 7)
Symbol
Parameter
Conditions
Typical
Limit
Units
(Note 9)
(Note 10 19)
(Limit)
tA
Acquisition Time
RSOURCE e 50X
35
35
m
s(min)
(Note 15)
tIA
Internal Acquisition Time
7(1fCLK)
7(1fCLK)
(max)
(when using WR Control Only)
tZA
Auto Zero Time a
33(1fCLK)
33(1fCLK) a 250 ns
(max)
Acquisition Time
fCLK e 175 MHz
188
1905
m
s(max)
tD(EOC)L
Delay from Hold Command
Using WR Control
200
350
ns(max)
to Falling Edge of EOC
Using S H Control
100
150
ns(max)
tCAL
Calibration Time
1399 (1fCLK)
1399 (1fCLK)
(max)
fCLK e 35 MHz
399
400
m
s(max)
tW(CAL)L
Calibration Pulse Width
(Note 16)
60
200
ns(min)
tW(WR)L
minimum WR Pulse Width
60
200
ns(min)
tACC
maximum Access Time
CL e 100 pF
(Delay from Falling Edge of
50
95
ns(max)
RD to Output Data Valid)
t0H t1H
TRI-STATE Control (Delay
RL e 1kX
from Rising Edge of RD
CL e 100 pF
30
70
ns(max)
to Hi-Z State)
tPD(INT)
maximum Delay from Falling Edge
100
175
ns(max)
of RD or WR to Reset of INT
tRR
Delay between Successive RD Pulses
30
60
ns(min)
Note 1
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is
functional but do not guarantee specific performance limits For guaranteed specifications and test conditions see the Electrical Characteristics The guaranteed
specifications apply only for the test conditions listed Some performance characteristics may degrade when the device is not operated under the listed test
conditions
Note 2
All voltages are measured with respect to AGND and DGND unless otherwise specified
Note 3
When the input voltage (VIN) at any pin exceeds the power supply rails (VIN k Vb or VIN l (AVCC or DVCC) the current at that pin should be limited to
5 mA The 20 mA maximum package input current rating allows the voltage at any four pins with an input current limit of 5 mA to simultaneously exceed the power
supply voltages
Note 4
The power dissipation of this device under normal operation should never exceed 191 mW (Quiescent Power Dissipation a 1 TTL Load on each digital
output) Caution should be taken not to exceed absolute maximum power rating when the device is operating in a severe fault condition (ex when any inputs or
outputs exceed the power supply) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMax (maximum junction
temperature) iJA (package junction to ambient thermal resistance) and TA (ambient temperature) The maximum allowable power dissipation at any temperature
is PDMax e (TJMax b TA) iJA or the number given in the Absolute Maximum Ratings whichever is lower For this device TJMax e 150 C and the typical thermal
resistance (iJA) of the ADC12451 with CMJ and CIJ suffixes when board mounted is 51 CW
Note 5
Human body model 100 pF discharged through a 15 kX resistor
Note 6
Two on-chip diodes are tied to the analog input as shown below Errors in the AD conversion can occur if these diodes are forward biased more than
50 mV This means that if AVCC and DVCC are minimum (475 VDC) and V
b
is maximum (b475 VDC) the analog input full-scale voltage must be s g48 VDC
TLH11025 – 4
5


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