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ADC0800 bảng dữ liệu(PDF) 4 Page - National Semiconductor (TI) |
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ADC0800 bảng dữ liệu(HTML) 4 Page - National Semiconductor (TI) |
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4 / 10 page  Application Hints (Continued) CMOS will satisfy this requirement but a pull-up resistor should be used for TTL logic inputs RE-START AND DATA VALID AFTER EOC The EOC line (pin 9) will be in the low state for a maximum of 40 clock periods to indicate ‘‘busy’’ A START pulse that occurs while the AD is BUSY will reset the SAR and start a new conversion with the EOC signal remaining in the low state until the end of this new conversion When the conver- sion is complete the EOC line will go to the high voltage state An additional 4 clock periods must be allowed to elapse after EOC goes high before a new conversion cycle is requested Start Conversion pulses that occur during this last 4 clock period interval may be ignored (see Figure 1 and 2 for high speed operation) This is a problem only for high conversion rates and keeping the number of conversions per second less than fCLOCK 44 automatically guarantees proper operation For example for an 800 kHz clock ap- proximately 18000 conversions per second are allowed The transfer of the new digital data to the output is initiated when EOC goes to the high voltage state POWER SUPPLIES Standard supplies are VSSea5V VGGeb12V and VDDe0V Device accuracy is dependent on stability of the reference voltage and has slight sensitivity to VSS VGG VDD has no effect on accuracy Noise spikes on the VSS and VGG supplies can cause improper conversion there- fore filtering each supply with a 47 mF tantalum capacitor is recommended CONTINUOUS CONVERSIONS AND LOGIC CONTROL Simply tying the EOC output to the Start Conversion input will allow continuous conversions but an oscillation on this line will exist during the first 4 clock periods after EOC goes high Adding a D flip-flop between EOC (D input) to Start Conversion (Q output) will prevent the oscillation and will allow a stopcontinuous control via the ‘‘clear’’ input To prevent missing a start pulse that may occur after EOC goes high and prior to the required 4 clock period time inter- val the circuit of Figure 1 can be used The RS latch can be set at any time and the 4-stage shift register delays the application of the start pulse to the AD by 4 clock periods The RS latch is reset 1 clock period after the AD EOC signal goes to the low voltage state This circuit also pro- vides a Start Conversion pulse to the AD which is 1 clock period wide A second control logic application circuit is shown in Figure 2 This allows an asynchronous start pulse of arbitrary length less than TC to continuously convert for a fixed high level and provides a single clock period start pulse to the AD The binary counter is loaded with a count of 11 when the start pulse to the AD appears Counting is inhibited until the EOC signal from the AD goes high A carry pulse is then generated 4 clock periods after EOC goes high and is used to reset the input RS latch This carry pulse can be used to indicate that the conversion is complete the data has transferred to the output buffers and the system is ready for a new conversion cycle TLH5670 – 3 FIGURE 1 Delaying an Asynchronous Start Pulse TLH5670 – 10 FIGURE 2 AD Control Logic 4 |
Số phần tương tự - ADC0800 |
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Mô tả tương tự - ADC0800 |
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