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LM25122-Q1
SNVSAF0A – DECEMBER 2015 – REVISED DECEMBER 2015
www.ti.com
Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
SLOPE
12
I
Slope compensation is programmed by a single resistor between SLOPE and the AGND.
Soft-start programming pin. An external capacitor and an internal 10-
μA current source set the ramp
SS
7
I
rate of the internal error amplifier reference during soft-start.
Switching node of the boost regulator. Connect to the bootstrap capacitor, the source terminal of the
SW
18
I/O
high-side N-channel MOSFET switch and the drain terminal of the low-side N-channel MOSFET
switch through short, low inductance paths.
The internal oscillator frequency is programmed by a single resistor between RT and the AGND.
The internal oscillator can be synchronized to an external clock by applying a positive pulse signal
SYNCIN/RT
8
I
into this SYNCIN pin. The recommended maximum internal oscillator frequency in master
configuration is 1.2 MHz which leads to 600 kHz maximum switching frequency.
Clock output pin. SYNCOUT provides 180º shifted clock output for an interleaved operation.
SYNCOUT
1
O
SYNCOUT pin can be left floating when it is not used. See Slave Mode and SYNCOUT section.
Undervoltage lockout programming pin. If the UVLO pin is below 0.4 V, the regulator is in the
shutdown mode with all functions disabled. If the UVLO pin voltage is greater than 0.4 V and below
1.2 V, the regulator is in standby mode with the VCC regulator operational and no switching at the
UVLO
6
I
HO and LO outputs. If the UVLO pin voltage is above 1.2 V, the startup sequence begins. A 10-
μA
current source at UVLO pin is enabled when UVLO exceeds 1.2 V and flows through the external
UVLO resistors to provide hysteresis. The UVLO pin should not be left floating.
VCC bias supply pin. Locally decouple to PGND using a low ESR/ESL capacitor located as close to
VCC
17
P/O/I
controller as possible.
Supply voltage input source for the VCC regulator. Connect to input capacitor and source power
VIN
5
P/I
supply connection with short, low impedance paths.
Exposed pad of the package. No internal electrical connections. Should be soldered to the large
EP
EP
N/A
ground plane to reduce thermal resistance.
6 Specifications
6.1 Absolute Maximum Ratings
(1)
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
Input
VIN, CSP, CSN
–0.3
50
V
BST to SW, FB, MODE, UVLO, OPT, VCC(2)
–0.3
15
V
SW
–5.0
60
V
BST
–0.3
75
V
SS, SLOPE, SYNCIN/RT
–0.3
7
V
CSP to CSN, PGND
–0.3
0.3
V
HO to SW
–0.3
BST to SW+0.3
V
Output(3)
LO
–0.3
VCC+0.3
V
COMP, RES, SYNCOUT
–0.3
7
V
Thermal
Junction Temperature
–40
150
ºC
Tstg
Storage temperature
–55
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Unless
otherwise specified, all voltages are referenced to AGND pin.
(2)
See Application Information when input supply voltage is less than the VCC voltage.
(3)
All output pins are not specified to have an external voltage applied.
4
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