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ADAU1451 bảng dữ liệu(PDF) 9 Page - Analog Devices

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ADAU1451 bảng dữ liệu(HTML) 9 Page - Analog Devices

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Data Sheet
ADAU1452/ADAU1451/ADAU1450
Auxiliary ADC
TA = −40°C to +105°C, DVDD = 1.2 V ± 5%, AVDD = 3.3 V ± 10%, IOVDD = 1.8 V − 10% to 3.3 V + 10%, unless otherwise noted.
Table 5.
Parameter
Min
Typ
Max
Unit
RESOLUTION
10
Bits
FULL-SCALE ANALOG INPUT
AVDD
V
NONLINEARITY
Integrated Nonlinearity (INL)
−2
+2
LSB
Differential Nonlinearity (DNL)
−2
+2
LSB
GAIN ERROR
−2
+2
LSB
INPUT IMPEDANCE
200
kΩ
SAMPLE RATE
fCORE/6144
Hz
TIMING SPECIFICATIONS
Master Clock Input
TA = −40°C to +105°C, DVDD = 1.2 V ± 5%, IOVDD = 1.8 V − 10% to 3.3 V + 10%, unless otherwise noted.
Table 6.
Parameter
Min
Max
Unit
Description
MASTER CLOCK INPUT (MCLK)
fMCLK
2.375
36
MHz
MCLK frequency
tMCLK
27.8
421
ns
MCLK period
tMCLKD
25
75
%
MCLK duty cycle
tMCLKH
0.25 × tMCLK
0.75 × tMCLK
ns
MCLK width high
tMCLKL
0.25 × tMCLK
0.75 × tMCLK
ns
MCLK width low
CLKOUT Jitter
12
106
ps
Cycle-to-cycle rms average
CORE CLOCK
fCORE
ADAU1452 and ADAU1451
152
294.912
MHz
System (DSP core) clock frequency; PLL
feedback divider ranges from 64 to 108
ADAU1450
76
147.456
MHz
System (DSP core) clock frequency; PLL
feedback divider ranges from 64 to 108
tCORE
ADAU1452 and ADAU1451
3.39
ns
System (DSP core) clock period
ADAU1450
6.78
ns
System (DSP core) clock period
MCLK
tMCLKH
tMCLKL
tMCLK
Figure 3. Master Clock Input Timing Specifications
Reset
TA = −40°C to +105°C, DVDD = 1.2 V ± 5%, IOVDD = 1.8 V − 10% to 3.3 V + 10%.
Table 7.
Parameter
Min
Max
Unit
Description
RESET
tWRST
10
ns
Reset pulse width low
RESET
tWRST
Figure 4. Reset Timing Specification
Rev. C | Page 9 of 180


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