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ADAU1452 bảng dữ liệu(PDF) 6 Page - Analog Devices |
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ADAU1452 bảng dữ liệu(HTML) 6 Page - Analog Devices |
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6 / 180 page  ADAU1452/ADAU1451/ADAU1450 Data Sheet SPECIFICATIONS AVDD = 3.3 V ± 10%, DVDD = 1.2 V ± 5%, PVDD = 3.3 V ± 10%, IOVDD = 1.8 V − 10% to 3.3 V + 10%, TA = 25°C, master clock input = 12.288 MHz, core clock (fCORE) = 294.912 MHz, I/O pins set to low drive setting, unless otherwise noted. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments POWER Supply Voltage Analog Voltage (AVDD) 2.97 3.3 3.63 V Supply for analog circuitry, including auxiliary ADC Digital Voltage (DVDD) 1.14 1.2 1.26 V Supply for digital circuitry, including the DSP core, ASRCs, and signal routing PLL Voltage (PVDD) 2.97 3.3 3.63 V Supply for phase-locked loop (PLL) circuitry I/O Supply Voltage (IOVDD) 1.71 3.3 3.63 V Supply for input/output circuitry, including pads and level shifters Supply Current Analog Current (AVDD) 1.5 1.73 2 mA Idle State 0 5 40 µA Power applied, chip not programmed Reset State 1.9 6.5 40 µA Power applied, RESET held low PLL Current (PVDD) 9.5 10 13 mA 12.288 MHz MCLK with default PLL settings Idle State 0 7.3 40 µA Power applied, PLL not configured Reset State 3.9 8.5 40 µA Power applied, RESET held low I/O Current (IOVDD) Dependent on the number of active serial ports, clock pins, and characteristics of external loads Operation State 53 mA IOVDD = 3.3 V; all serial ports are clock masters 22 mA IOVDD = 1.8 V; all serial ports are clock masters Power-Down State 0.3 2.5 mA IOVDD = 1.8 V − 10% to 3.3 V + 10% Digital Current (DVDD) Operation State, ADAU1452 Maximum Program 350 415 mA Typical Program 100 mA Test program includes 16-channel I/O, 10-band EQ per channel, all ASRCs active Minimal Program 85 mA Test program includes 2-channel I/O, 10-band EQ per channel Operation State, ADAU1451 Maximum Program 350 415 mA Typical Program 100 mA Test program includes 16-channel I/O, 10-band EQ per channel, all ASRCs active Minimal Program 85 mA Test program includes 2-channel I/O, 10-band EQ per channel Operation State, ADAU1450 Maximum Program 125 250 mA fCORE = 147.456 MHz Typical Program 65 mA Test program includes 16-channel I/O, 10-band EQ per channel, fCORE = 147.456 MHz Minimal Program 55 mA Test program includes 2-channel I/O, 10-band EQ per channel, fCORE = 147.456 MHz Idle State 20 95 mA Power applied, DSP not enabled Reset State 20 95 mA Power applied, RESET held low ASYNCHRONOUS SAMPLE RATE CONVERTERS Dynamic Range 139 dB A-weighted, 20 Hz to 20 kHz I/O Sample Rate 6 192 kHz I/O Sample Rate Ratio 1:8 7.75:1 THD + N −120 dB CRYSTAL OSCILLATOR Transconductance 8.3 10.6 13.4 mS REGULATOR DVDD Voltage 1.14 1.2 V Regulator maintains typical output voltage up to a maximum 800 mA load; IOVDD = 1.8 V − 10% to 3.3 V + 10% Rev. C | Page 6 of 180 |
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