AD6679BBPZ-500 datasheet(9/81 Pages) AD

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Data Sheet

AD6679

Rev. B | Page 9 of 81

Parameter

Temperature

Min

Typ

Max

Unit

Wake-Up Time6

Standby

25°C

1

ms

Power-Down6

25°C

4

ms

APERTURE

Aperture Delay (tA)

Full

530

ps

Aperture Uncertainty (Jitter, tJ)

Full

55

fs rms

Out of Range Recovery Time

Full

1

Clock cycles

1

The maximum sample rate is the clock rate after the divider.

2

The minimum sample rate operates at 300 MSPS with L = 2 or L = 1.

3

This specification is valid for parallel interleaved, channel multiplexed, and byte mode output modes.

4

This specification is valid for byte mode output mode only.

5

Add this value to the pipeline latency specification to achieve total latency through the AD6679.

6

Wake-up time is defined as the time required to return to normal operation from power-down mode or standby mode.

TIMING SPECIFICATIONS

Table 5.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

CLK± to SYNC± TIMING REQUIREMENTS

tSU_SR

Device clock to SYNC± setup time

117

ps

tH_SR

Device clock to SYNC± hold time

−96

ps

SPI TIMING REQUIREMENTS

See Figure 3

tDS

Setup time between the data and the rising edge of SCLK

2

ns

tDH

Hold time between the data and the rising edge of SCLK

2

ns

tCLK

Period of the SCLK

40

ns

tS

Setup time between CSB and SCLK

2

ns

tH

Hold time between CSB and SCLK

2

ns

tHIGH

Minimum period that SCLK is in a logic high state

10

ns

tLOW

Minimum period that SCLK is in a logic low state

10

ns

tACCESS

Maximum time delay between falling edge of SCLK and output

data valid for a read operation

6

10

ns

tDIS_SDIO

Time required for the SDIO pin to switch from an output to an

input relative to the SCLK rising edge (not shown in Figure 3)

10

ns

Timing Diagrams

CLK+

CLK–

SYNC+

SYNC–

tSU_SR

tH_SR

Figure 2. SYNC± Setup and Hold Timing

tACCESS

DON’T CARE

SDIO

SCLK

tS

tDH

tCLK

tDS

tH

R/W

A14

A13

A12

A11

A10

A9

A8

A7

D7

D6

D3

D2

D1

D0

tLOW

tHIGH

CSB

Figure 3. Serial Port Interface Timing Diagram

Số phần tương tự - AD6679BBPZ-500

nhà sản xuất	tên linh kiện	bảng dữ liệu	Giải thích chi tiết về linh kiện
Analog Devices	AD6679BBPZ-500	1Mb / 82P	135 MHz BW IF Diversity Receiver

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Mô tả tương tự - AD6679BBPZ-500

nhà sản xuất	tên linh kiện	bảng dữ liệu	Giải thích chi tiết về linh kiện
Analog Devices	AD6679	1Mb / 82P	135 MHz BW IF Diversity Receiver
	AD6674	4Mb / 97P	385 MHz BW IF Diversity Receiver
	AD6674	2Mb / 91P	385 MHz BW IF Diversity Receiver
	AD6684	2Mb / 107P	135 MHz Quad IF Receiver
	AD6655ABCPZ-80	2Mb / 88P	IF Diversity Receiver REV. A
	AD6649	1Mb / 41P	IF Diversity Receiver
	AD6655	2Mb / 85P	IF Diversity Receiver
	AD6655	2Mb / 84P	IF Diversity Receiver REV. 0
	AD6653	2Mb / 80P	IF Diversity Receiver REV. 0
	AD6649	1Mb / 40P	IF Diversity Receiver

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