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SN74AHC139PWR bảng dữ liệu(PDF) 2 Page - Texas Instruments |
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SN74AHC139PWR bảng dữ liệu(HTML) 2 Page - Texas Instruments |
2 / 22 page Select Inputs Select Inputs 2B 2A 2G 1B 1A 1G Data Outputs 2Y3 2Y2 2Y1 2Y0 1Y3 1Y2 1Y1 1Y0 1 2 3 15 14 13 4 5 6 7 12 11 10 9 SN74AHC139 SN54AHC139 SCLS259L – DECEMBER 1995 – REVISED JUNE 2013 www.ti.com LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC) Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT Supply voltage range, VCC –0.5 to 7 V Input voltage range, VI (2) –0.5 to 7 V Output voltage range, VO (2) –0.5 to VCC + 0.5 V Input clamp current, IIK (VI < 0) –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA Continuous output current, IO (VO = 0 to VCC) ±25 mA Continuous current through VCC or GND ±75 mA D package(3) 73 DB package(3) 82 DGV package(3) 120 Package thermal impedance, θJA N package(3) 67 °C/W NS package(3) 64 PW package(3) 108 RGY package(4) 39 Storage temperature range, Tstg –65 to 150 °C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) The package thermal impedance is calculated in accordance with JESD 51-7. (4) The package thermal impedance is calculated in accordance with JESD 51-5 2 Submit Documentation Feedback Copyright © 1995–2013, Texas Instruments Incorporated Product Folder Links: SN74AHC139 SN54AHC139 |
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