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PEF2256H bảng dữ liệu(PDF) 5 Page - Infineon Technologies AG

tên linh kiện PEF2256H
Giải thích chi tiết về linh kiện  E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
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nhà sản xuất  INFINEON [Infineon Technologies AG]
Trang chủ  http://www.infineon.com
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FALC®56
PEF 2256 H/E
Table of Contents
Page
User’s Manual
5
DS1.1, 2003-10-23
Hardware Description
4.4.7.1
HDLC or LAPD access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.4.7.2
Support of Signaling System #7 . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.4.7.3
Sa-Bit Access (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.4.7.4
Channel Associated Signaling CAS (E1, serial mode) . . . . . . . . . . 104
4.4.7.5
Channel Associated Signaling CAS (E1, µP access mode) . . . . . . 104
4.5
System Interface in E1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.5.1
Receive System Interface (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.5.1.1
Receive Offset Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.5.2
Transmit System Interface (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.5.2.1
Transmit Offset Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.5.3
Time Slot Assigner (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
4.6
Test Functions (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.6.1
Pseudo-Random Binary Sequence Generation and Monitor . . . . . . . . 117
4.6.2
Remote Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.6.3
Payload Loop-Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
4.6.4
Local Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4.6.5
Single Channel Loop-Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.6.6
Alarm Simulation (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
4.6.7
Single Bit Defect Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5
Functional Description T1/J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.1
Receive Path in T1/J1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.1.1
Receive Line Interface (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.1.2
Receive Short and Long-Haul Interface (T1/J1) . . . . . . . . . . . . . . . . . 122
5.1.3
Receive Equalization Network (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.1.4
Receive Line Attenuation Indication (T1/J1) . . . . . . . . . . . . . . . . . . . . 123
5.1.5
Receive Clock and Data Recovery (T1/J1) . . . . . . . . . . . . . . . . . . . . . 123
5.1.6
Receive Line Coding (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.1.7
Receive Line Termination (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.1.8
Receive Line Monitoring Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.1.9
Loss-of-Signal Detection (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.1.10
Receive Jitter Attenuator (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
5.1.11
Jitter Tolerance (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.1.12
Output Jitter (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.1.13
Framer/Synchronizer (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.1.14
Receive Elastic Buffer (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.1.15
Receive Signaling Controller (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.1.15.1
HDLC or LAPD Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.1.15.2
Support of Signaling System #7 . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.1.15.3
CAS Bit-Robbing (T1/J1, serial mode) . . . . . . . . . . . . . . . . . . . . . . . 141
5.1.15.4
CAS Bit-Robbing (T1/J1, µP access mode) . . . . . . . . . . . . . . . . . . . 141
5.1.15.5
Bit Oriented Messages in ESF-DL Channel (T1/J1) . . . . . . . . . . . . 141
5.1.15.6
4 kbit/s Data Link Access in F72 Format (T1/J1) . . . . . . . . . . . . . . . 142


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