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SN74AHC541DW bảng dữ liệu(PDF) 11 Page - Texas Instruments |
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SN74AHC541DW bảng dữ liệu(HTML) 11 Page - Texas Instruments |
11 / 29 page Vcc Unused Input Input Output Input Unused Input Output 0 1 2 3 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Time (ns) A1 Y1 C001 SN74AHC541, SN54AHC541 www.ti.com SCLS261O – OCTOBER 1995 – REVISED SEPTEMBER 2015 Typical Application (continued) 9.2.3 Application Curve Vcc = 3.3 V, CL = 15 pF, TA = 25°C Figure 4. Simulated Propagation Delay From Input (A1) to Output (Y1) 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions table. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, 0.1 μF is recommended. If there are multiple VCC terminals then 0.01 μF or 0.022 μF is recommended for each power terminal. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results. 11 Layout 11.1 Layout Guidelines When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used, or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified in the Figure 5 are rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when asserted. This will not disable the input section of the I/Os so they also cannot float when disabled. 11.2 Layout Example Figure 5. Layout Diagram Copyright © 1995–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: SN74AHC541 SN54AHC541 |
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