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SN74AHC1G09DCKR bảng dữ liệu(PDF) 10 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  Single 2?밒nput Positive-AND Gate With Open-Drain Output
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VCC
Unused Input
Input
Output
Output
Input
Unused Input
Time (ns)
20
0
2
4
6
8
10
12
14
16
18
±1.5 V
±1 V
0 V
0.5 V
1 V
1.5 V
2 V
2.5 V
3.5 V
4 V
4.5 V
5 V
3 V
5.5 V
HC
VI
AC
AHC1G09
SN74AHC1G09
SCLS724C – MAY 2011 – REVISED JANUARY 2016
www.ti.com
Typical Application (continued)
9.2.3 Application Curve
VCC = 5 V, Load = 50 Ω / 50 pF
Figure 4. ICC vs Input Voltage
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
Recommended Operating Conditions.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-
μF capacitor is recommended; if there are multiple VCC pins then a 0.01-μF or 0.022-μF capacitor is
recommended for each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies
of noise. 0.1-
μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as
close to the power pin as possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs must not ever float. In many cases, functions or parts of functions of
digital logic devices are unused (for example, when only two inputs of a triple-input AND gate are used, or only 3
of the 4 buffer gates are used). Such input pins must not be left unconnected because the undefined voltages at
the outside connections result in undefined operational states.
The following are the rules that must be observed under all circumstances:
All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from
floating.
The logic level that should be applied to any particular unused input depends on the function of the device.
Generally they will be tied to GND or VCC, whichever make more sense or is more convenient.
11.2 Layout Example
Figure 5. Layout Diagram
10
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