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LMH1218RTWT bảng dữ liệu(PDF) 7 Page - Texas Instruments |
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LMH1218RTWT bảng dữ liệu(HTML) 7 Page - Texas Instruments |
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7 / 57 page  7 LMH1218 www.ti.com SNLS474B – FEBRUARY 2015 – REVISED FEBRUARY 2016 Product Folder Links: LMH1218 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) No heat sink is assumed for these estimations. Depending on the application, a heat sink, faster air flow, and/or reduced ambient temperature ( < 85ºC) may be required in order to maintain the maximum junction temperature specified in Electrical Characteristics. 6.4 Thermal Information THERMAL METRIC(1)(2) RTWA0024A UNIT 24 PINS RθJA Junction-to-ambient thermal resistance 34 °C/W RθJC(top) Junction-to-case (top) thermal resistance 31.4 RθJB Junction-to-board thermal resistance 11.8 ψJT Junction-to-top characterization parameter 0.3 ψJB Junction-to-board characterization parameter 11.8 RθJC(bot) Junction-to-case (bottom) thermal resistance 2.7 6.5 Electrical Characteristics Over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER PD Power dissipation Locked 75 Ω OUT0 only (800 mVpp), EOM powered down 300 mW Locked OUT1 only (600 mVpp, diff), EOM powered down 195 mW Transient power during CDR lock acquisition, 75 Ω OUT0 and OUT1 powered up, EOM powered down 400 500 mW PD_RAW Power dissipation in force RAW mode (CDR bypass) EQ bypass, OUT0 720mVpp, OUT1 600mVpp IN0 to OUT0 and OUT1 or IN1 to OUT0 and OUT1 195 mW IN0 to OUT0, OUT1 powered down 160 mW IN1 to OUT1, OUT0 powered down 80 mW 4-LEVEL INPUT and 2.5 V LVCMOS DC SPECIFICATIONS VIH High level input voltage 4-level input (MODE_SEL, ADDR0/1, ENABLE pins) 0.95*VDD V VIF Float level input voltage 4-level input (MODE_SEL, ADDR0/1, ENABLE pins) 0.67*VDD V VI20K 20K to GND input voltage 4-level input (MODE_SEL, ADDR0/1, ENABLE pins) 0.33*VDD V VIL Low level input voltage 4-level input (MODE_SEL, ADDR0/1, ENABLE pins) 0.1 V VOH High level output voltage IOH = -3 mA 2 V VOL Low level output voltage IOL = 3 mA 0.4 V IIH Input high leakage current Vinput = VDD SPI Mode: LVCMOS (SPI_SCK, SPI_SS_N) pins 15 µA SMBus Mode: LVCMOS (SMB_SDA, SMB_SCL) pins 15 µA SMBus Mode: 4-Levels (ADDR0, ADDR1) pins 20 44 80 µA 4-Levels (MODE_SEL, ENABLE) pins 20 44 80 µA |
Số phần tương tự - LMH1218RTWT |
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Mô tả tương tự - LMH1218RTWT |
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