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FDC2114RGHR bảng dữ liệu(PDF) 7 Page - Texas Instruments

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tên linh kiện FDC2114RGHR
Giải thích chi tiết về linh kiện  Capacitance-to-Digital Converter for Proximity Level Sensing Applications
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nhà sản xuất  TI1 [Texas Instruments]
Trang chủ  http://www.ti.com
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FDC2114RGHR bảng dữ liệu(HTML) 7 Page - Texas Instruments

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SCL
SDA
tHD;STA
tLOW
tr
tHD;DAT
tHIGH
tf
tSU;DAT
tSU;STA
tSU;STO
tf
START
REPEATED
START
STOP
tHD;STA
START
tSP
tr
tBUF
FDC2212, FDC2214, FDC2112, FDC2114
www.ti.com
SNOSCZ5A – JUNE 2015 – REVISED JUNE 2015
Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for TA = 25°C, VDD = 3.3 V
(1)
PARAMETER
TEST CONDITIONS(2)
MIN(3)
TYP(4)
MAX(3)
UNIT
VCLKIN_HI
CLKIN high voltage threshold
0.7*VDD
V
fINTCLK
Internal master clock frequency
35
43.4
55
MHz
range
TCf_int_μ
Internal master clock temperature
–13
ppm/°C
coefficient mean
8.6 Timing Requirements
MIN
NOM
MAX
UNIT
tSDWAKEUP
Wake-up time from SD high-low transition to I2C readback
2
ms
tSLEEPWAKEUP Wake-up time from sleep mode
0.05
ms
tWD-TIMEOUT
Sensor recovery time (after watchdog timeout)
5.2
ms
I2C TIMING CHARACTERISTICS
fSCL
Clock frequency
10
400
kHz
tLOW
Clock low time
1.3
μs
tHIGH
Clock high time
0.6
μs
Hold time (repeated) START condition: after this period, the first clock
tHD;STA
0.6
μs
pulse is generated
tSU;STA
Setup time for a repeated START condition
0.6
μs
tHD;DAT
Data hold time
0
μs
tSU;DAT
Data setup time
100
ns
tSU;STO
Setup time for STOP condition
0.6
μs
tBUF
Bus free time between a STOP and START condition
1.3
μs
tVD;DAT
Data valid time
0.9
μs
tVD;ACK
Data valid acknowledge time
0.9
μs
tSP
Pulse width of spikes that must be suppressed by the input filter(1)
50
ns
(1)
This parameter is specified by design and/or characterization and is not tested in production.
Figure 1. I2C Timing
Copyright © 2015, Texas Instruments Incorporated
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Product Folder Links: FDC2212 FDC2214 FDC2112 FDC2114


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