ADS8684AIDBTR datasheet(11/80 Pages) TI1

tên linh kiện	ADS8684AIDBTR

Giải thích chi tiết về linh kiện	4- and 8-Channel, Single-Supply, SAR ADCs

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nhà sản xuất	TI1 [Texas Instruments]

Trang chủ	http://www.ti.com

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11 / 80 page

1

2

14

15

16

17

23

24

25

26

27

28

29

30

SCLK

CS

D9

#2

D8

#2

D7

#2

D6

#2

D5

#2

D4

#2

SDO

tSU_CSCK

tDZ_CSDO

tHT_CKDO

tSU_DOCK

tDZ_CSDO

Sample

N

Sample

N + 1

tACQ

tCONV

tS

Data from sample N

tPH_CS

31

32

D15

#2

D14

#2

18

D3

#2

D2

#2

D1

#2

D0

#2

B15

B14

B2

B1

B0

X

SDI

X

tPH_CK

tPL_CK

tSCLK

tSU_DICK

tHT_CKDI

tD_CKCS

7

8

9

B9

B8

B7

B10

B3

D9

#1

D8

#1

D7

#1

D6

#1

D5

#1

D4

#1

DAISY

D15

#1

D14

#1

D3

#1

D2

#1

D1

#1

D0

#1

tHT_CKDSY

tSU_DSYCK

ADS8684A, ADS8688A

www.ti.com

SBAS680 – JULY 2015

7.6 Timing Requirements: Serial Interface

Minimum and maximum specifications are at TA = –40°C to 125°C. Typical specifications are at TA = 25°C.

AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), SDO load = 20 pF, and fSAMPLE = 500 kSPS, unless otherwise noted.

MIN

TYP

MAX

UNIT

TIMING SPECIFICATIONS

fS

Sampling frequency (fCLK = max)

500

kSPS

tS

ADC cycle time period (fCLK = max)

2

µs

fSCLK

Serial clock frequency (fS = max)

17

MHz

tSCLK

Serial clock time period (fS = max)

59

ns

tCONV

Conversion time

850

ns

tDZ_CSDO

Delay time: CS falling to data enable

10

ns

tD_CKCS

Delay time: last SCLK falling to CS rising

10

ns

tDZ_CSDO

Delay time: CS rising to SDO going to 3-state

10

ns

TIMING REQUIREMENTS

tACQ

Acquisition time

1150

ns

tPH_CK

Clock high time

0.4

0.6

tSCLK

tPL_CK

Clock low time

0.4

0.6

tSCLK

tPH_CS

CS high time

30

ns

tSU_CSCK

Setup time: CS falling to SCLK falling

30

ns

tHT_CKDO

Hold time: SCLK falling to (previous) data valid on SDO

10

ns

tSU_DOCK

Setup time: SDO data valid to SCLK falling

25

ns

tSU_DICK

Setup time: SDI data valid to SCLK falling

5

ns

tHT_CKDI

Hold time: SCLK falling to (previous) data valid on SDI

5

ns

tSU_DSYCK

Setup time: DAISY data valid to SCLK falling

5

ns

tHT_CKDSY

Hold time: SCLK falling to (previous) data valid on DAISY

5

ns

Figure 1. Serial Interface Timing Diagram

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Product Folder Links: ADS8684A ADS8688A

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