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ADC0804LCN/NOPB bảng dữ liệu(PDF) 11 Page - Texas Instruments

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ADC0801, ADC0802, ADC0803, ADC0804, ADC0805
www.ti.com
SNOSBI1C – NOVEMBER 2009 – REVISED JUNE 2015
8 Detailed Description
8.1 Overview
The ADC0801 series are versatile 8-Bit µP compatible general purpose ADC converters operate on single 5-V
supply. These devices are treated as a memory location or I/O port to a micro-processor system without
additional interface logic. The outputs are Tri-state latched which facilitate interfacing to micro-processor control
bus. The converter is designed with a differential potentiometric ladder, a circuit equivalent of the 256R network.
It contains analog switches sequenced by successive approximation logic. A functional diagram of the ADC
converter is shown in Functional Block Diagram. All of the package pinouts are shown and the major logic control
paths are drawn in heavier weight lines. The differential analog voltage input has good common mode-rejection
and permits offsetting the analog zero-input voltage value. Moreover, the input reference voltage can be adjusted
to allow encoding small analog voltage span to the full 8-bits resolution. To ensure start-up under all possible
conditions, an external WR pulse is required during the first power-up cycle.
Using a SAR logic the most significant bit is tested first and after 8 comparisons (64 clock cycles) a digital 8-bit
binary code (1111 1111 = full-scale) is transferred to an output latch and then an interrupt is asserted (INTR
makes a high-to-low transition). A conversion in process can be interrupted by issuing a second start command.
The device may be operated in the free-running mode by connecting INTR to the WR input with CS=0.
On the high-to-low transition of the WR input the internal SAR latches and the shift register stages are reset. As
long as the CS input and WR input remain low, the ADC will remain in a reset state. Conversion will start from 1
to 8 clock periods after at least one of these inputs makes a low-to-high transition.
The converter is started by having CS and WR simultaneously low. This sets the start flip-flop (F/F) and the
resulting “1” level resets the 8-bit shift register, resets the Interrupt (INTR) F/F and inputs a “1” to the D flop,
F/F1, which is at the input end of the 8-bit shift register. Internal clock signals then transfer this “1” to the Q
output of F/F1. The AND gate, G1, combines this “1” output with a clock signal to provide a reset signal to the
start F/F. If the set signal is no longer present (either WR or CS is a “1”) the start F/F is reset and the 8-bit shift
register then can have the “1” clocked in, which starts the conversion process. If the set signal were to still be
present, this reset pulse would have no effect (both outputs of the start F/F would momentarily be at a “1” level)
and the 8-bit shift register would continue to be held in the reset mode. This logic therefore allows for wide CS
and WR signals and the converter will start after at least one of these signals returns high and the internal clocks
again provide a reset signal for the start F/F.
After the “1” is clocked through the 8-bit shift register (which completes the SAR search) it appears as the input
to the D-type latch, LATCH 1. As soon as this “1” is output from the shift register, the AND gate, G2, causes the
new digital word to transfer to the Tri-state output latches. When LATCH 1 is subsequently enabled, the Q output
makes a high-to-low transition which causes the INTR F/F to set. An inverting buffer then supplies the INTR input
signal.
Note this SET control of the INTR F/F remains low for 8 of the external clock periods (as the internal clocks run
at 1/8 of the frequency of the external clock). If the data output is continuously enabled (CS and RD both held
low), the INTR output will still signal the end of conversion (by a high-to-low transition), because the SET input
can control the Q output of the INTR F/F even though the RESET input is constantly at a M "1M " level in this
operating mode. This INTR output will therefore stay low for the duration of the SET signal, which is 8 periods of
the external clock frequency (assuming the ADC is not started during this interval).
When operating in the free-running or continuous conversion mode (INTR pin tied to WR and CS wired low – see
Continuous Conversions), the START F/F is SET by the high-to-low transition of the INTR signal. This resets the
SHIFT REGISTER which causes the input to the D-type latch, LATCH 1, to go low. As the latch enable input is
still present, the Q output will go high, which then allows the INTR F/F to be RESET. This reduces the width of
the resulting INTR output pulse to only a few propagation delays (approximately 300 ns).
When data is to be read, the combination of both CS and RD being low will cause the INTR F/F to be reset and
the Tri-state output latches will be enabled to provide the 8-bit digital outputs.
Copyright © 2009–2015, Texas Instruments Incorporated
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Product Folder Links: ADC0801 ADC0802 ADC0803 ADC0804 ADC0805


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