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ADS42JB46IRGC25 bảng dữ liệu(PDF) 1 Page - Texas Instruments |
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ADS42JB46IRGC25 bảng dữ liệu(HTML) 1 Page - Texas Instruments |
1 / 63 page −120 −100 −80 −60 −40 −20 0 0 20 40 60 80 Frequency (MHz) FIN = 170 MHz SFDR = 92 dBc SNR = 73 dBFS SINAD = 72.9 dBFS THD = 91 dBc SFDR Non HD2, HD3 = 100 dBc G002 CLKINP, M CLKIN INAP, M INA Device Configuration Common Mode VCM DA1P, M DA1 DB1P, DB1M DA0P, M DA0 DB0P, DB0M 14-, 16-Bit ADC JESD204B Digital INBP, M INB Digital Block Gain Test Modes JESD204B Digital Digital Block Gain Test Modes Device SYSREFP, M SYSREF PLL x10, x20 SYNC~P, M SYNC~ Divide by 1, 2, 4 OVRA OVRB Delay 14-, 16-Bit ADC Product Folder Sample & Buy Technical Documents Tools & Software Support & Community ADS42JB46 SBAS621B – JULY 2013 – REVISED SEPTEMBER 2015 ADS42JB46 Dual-Channel, 14-Bit, 160-MSPS Analog-to-Digital Converter 1 Features 2 Applications 1 • Dual-Channel ADCs • Communication and Cable Infrastructure • 14-Bit Resolution • Multi-Carrier, Multimode Cellular Receivers • Maximum Clock Rate: 160 MSPS • Radar and Smart Antenna Arrays • JESD204B Serial Interface • Broadband Wireless • Test and Measurement Systems – Subclass 0, 1, 2 Compliant • Software-Defined and Diversity Radios – Up to 3.125 Gbps • Microwave and Dual-Channel I/Q Receivers – Two- and Four-Lane Support • Repeaters • Analog Input Buffer with High-Impedance Input • Power Amplifier Linearization • Flexible Input Clock Buffer: Divide-by-1, -2, and -4 3 Description • Differential Full-Scale Input: 2 VPP and 2.5 VPP The ADS42JB46 is a high-linearity, dual-channel, 14- (Register Programmable) bit, 160-MSPS, analog-to-digital converter (ADC). • Package: 9-mm × 9-mm QFN-64 This device supports the JESD204B serial interface • Power Dissipation: 679 mW/Ch with data rates up to 3.125 Gbps. The buffered analog input provides uniform input impedance • Aperture Jitter: 85 fS rms across a wide frequency range while minimizing • Internal Dither sample-and-hold glitch energy, thus making driving • Channel Isolation: 100 dB analog inputs up to very high input frequencies easy. • Performance: A sampling clock divider allows more flexibility for system clock architecture design. The device – fIN = 170 MHz at 2 VPP, –1 dBFS employs internal dither algorithms to provide excellent – SNR: 72.9 dBFS spurious-free dynamic range (SFDR) over a large – SFDR: 90 dBc for HD2, HD3 input frequency range. – SFDR: 100 dBc for Non HD2, HD3 Device Information(1) – fIN = 170 MHz at 2.5 VPP, –1 dBFS PART NUMBER PACKAGE BODY SIZE (NOM) – SNR: 74.2 dBFS ADS42JB46 VQFN (64) 9.00 mm × 9.00 mm – SFDR: 84 dBc for HD2, HD3 and (1) For all available packages, see the orderable addendum at 95 dBc for Non HD2, HD3 the end of the data sheet. Simplified Schematic FFT for 170-MHz Input Signal Sampled at 160 MSPS 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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