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ADC3441 bảng dữ liệu(PDF) 5 Page - Texas Instruments |
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ADC3441 bảng dữ liệu(HTML) 5 Page - Texas Instruments |
5 / 83 page ADC3441, ADC3442, ADC3443, ADC3444 www.ti.com SBAS670A – JULY 2014 – REVISED OCTOBER 2015 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Analog supply voltage range, AVDD –0.3 2.1 V Digital supply voltage range, DVDD –0.3 2.1 V INAP, INBP, INAM, INBM –0.3 min (1.9, AVDD + 0.3) CLKP, CLKM –0.3 AVDD + 0.3 Voltage applied to V input pins SYSREFP, SYSREFM –0.3 AVDD + 0.3 SCLK, SEN, SDATA, RESET, PDN –0.3 3.9 Operating free-air, TA –40 85 Temperature Operating junction, TJ 125 ºC Storage, Tstg –65 150 (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions (1) over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT SUPPLIES AVDD Analog supply voltage range 1.7 1.8 1.9 V DVDD Digital supply voltage range 1.7 1.8 1.9 V ANALOG INPUT For input frequencies < 450 MHz 2 VID Differential input voltage VPP For input frequencies < 600 MHz 1 VIC Input common-mode voltage VCM ± 0.025 V CLOCK INPUT Input clock frequency Sampling clock frequency 15(2) 125(3) MSPS Sine wave, ac-coupled 0.2 1.5 Input clock amplitude (differential) LPECL, ac-coupled 1.6 VPP LVDS, ac-coupled 0.7 Input clock duty cycle 35% 50% 65% Input clock common-mode voltage 0.95 V DIGITAL OUTPUTS CLOAD Maximum external load capacitance from each output pin to GND 3.3 pF RLOAD Single-ended load resistance 100 Ω (1) After power-up, use only the RESET pin to reset the device for the first time; see the Register Initialization section for details. (2) See Table 3 for details. (3) With the clock divider enabled by default for divide-by-1. Maximum sampling clock frequency for the divide-by-4 option is 500 MSPS. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: ADC3441 ADC3442 ADC3443 ADC3444 |
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