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ADC12D1000RFIUT/NOPB bảng dữ liệu(PDF) 10 Page - Texas Instruments

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tên linh kiện ADC12D1000RFIUT/NOPB
Giải thích chi tiết về linh kiện  12-Bit, 3.2-GSPS and 2-GSPS RF-Sampling ADC
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VA
GND
GND
VA
100 k:
GND
VA
100 k:
GND
VA
100 k:
GND
VA
50 k:
ADC12D1000RF, ADC12D1600RF
SNAS519H – JULY 2011 – REVISED AUGUST 2015
www.ti.com
Table 3-2. Control and Status Balls (continued)
PIN
I/O
EQUIVALENT CIRCUIT
DESCRIPTION
NAME
NO.
Power Down I- and Q-channel. Setting
either input to logic-high powers down the
respective I- or Q-channel. Setting either
input to logic-low brings the respective I-
or Q-channel to a operational state after a
PDI
U3
finite time delay. This pin is active in both
I
PDQ
V3
ECM and Non-ECM. In ECM, each Pin is
logically OR'd with its respective Bit.
Therefore, either this pin or the PDI and
PDQ Bit in the Control Register can be
used to power down the I- and Q-channel
(Addr: 0h, Bit 11 and Bit 10), respectively.
Serial Clock. In ECM, serial data is shifted
into and out of the device synchronously
to this clock signal. This clock may be
SCLK
C5
I
disabled and held logic-low, as long as
timing specifications are not violated
when the clock is enabled or disabled.
Serial Chip Select bar. In ECM, when this
signal is asserted (logic-low), SCLK is
used to clock in serial data which is
SCS
C4
I
present on SDI and to source serial data
on SDO. When this signal is deasserted
(logic-high), SDI is ignored and SDO is in
tri-stated.
Serial Data-In. In ECM, serial data is
SDI
B4
I
shifted into the device on this pin while
SCS signal is asserted (logic-low).
Serial Data-Out. In ECM, serial data is
shifted out of the device on this pin while
SDO
A3
O
SCS signal is asserted (logic-low). This
output is tri-stated when SCS is
deasserted.
10
Pin Configuration and Functions
Copyright © 2011–2015, Texas Instruments Incorporated
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Product Folder Links: ADC12D1000RF ADC12D1600RF


Số phần tương tự - ADC12D1000RFIUT/NOPB

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