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ADC12D1000CIUT bảng dữ liệu(PDF) 7 Page - Texas Instruments

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GND
VA
GND
VA
VA
GND
GND
VA
GND
VA
ADC12D1000, ADC12D1600
www.ti.com
SNAS480N – MAY 2010 – REVISED AUGUST 2015
Pin Functions: Control and Status Balls
PIN
I/O
EQUIVALENT CIRCUIT
DESCRIPTION
NAME
NO.
Calibration cycle initiate. The user can command
the device to execute a self-calibration cycle by
holding this input high a minimum of tCAL_H after
having held it low a minimum of tCAL_L. If this input
is held high at the time of power on, the automatic
power-on calibration cycle is inhibited until this
CAL
D6
I
input is cycled low-then-high. This pin is active in
both ECM and Non-ECM. In ECM, this pin is
logically OR'd with the CAL Bit (Addr: 0h, Bit 15) in
the Control Register. Therefore, both pin and bit
must be set low and then either can be set high to
execute an on-command calibration.
Calibration Delay select. By setting this input logic-
high or logic-low, the user can select the device to
wait a longer or shorter amount of time,
CalDly
V4
I
respectively, before the automatic power-on self-
calibration is initiated. This feature is pin-controlled
only and is always active during ECM and Non-
ECM.
Calibration Running indication. This output is logic-
CalRun
B5
O
high while the calibration sequence is executing.
This output is logic-low otherwise.
DDR Phase select. This input, when logic-low,
selects the 0° Data-to-DCLK phase relationship.
When logic-high, it selects the 90° Data-to-DCLK
phase relationship, that is, the DCLK transition
indicates the middle of the valid data outputs. This
DDRPh
W4
I
pin only has an effect when the chip is in 1:2
Demuxed Mode, that is, the NDM pin is set to
logic-low. In ECM, this input is ignored and the
DDR phase is selected through the Control
Register by the DPS Bit (Addr: 0h, Bit 14); the
default is 0° Mode.
Dual Edge Sampling (DES) Mode select. In the
Non-Extended Control Mode (Non-ECM), when this
input is set to logic-high, the DES Mode of
operation is selected, meaning that the VinI input is
sampled by both channels in a time-interleaved
manner. The VinQ input is ignored. When this input
DES
V5
I
is set to logic-low, the device is in Non-DES Mode,
that is, the I- and Q-channels operate
independently. In the Extended Control Mode
(ECM), this input is ignored and DES Mode
selection is controlled through the Control Register
by the DES Bit (Addr: 0h, Bit 7); default is Non-
DES Mode operation.
Do Not Connect. These pins are used for internal
D1, D7, E3,
DNC
NONE
purposes and should not be connected, that is, left
F4, W3, U7
floating. Do not ground.
Copyright © 2010–2015, Texas Instruments Incorporated
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