công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
ADC12D1000 bảng dữ liệu(PDF) 8 Page - Texas Instruments |
|
ADC12D1000 bảng dữ liệu(HTML) 8 Page - Texas Instruments |
8 / 86 page GND VA 100 k: GND VA 50 k: GND VA GND VA GND VA 50 k: ADC12D1000, ADC12D1600 SNAS480N – MAY 2010 – REVISED AUGUST 2015 www.ti.com Pin Functions: Control and Status Balls (continued) PIN I/O EQUIVALENT CIRCUIT DESCRIPTION NAME NO. Extended Control Enable bar. Extended feature control through the SPI interface is enabled when this signal is asserted (logic-low). In this case, most of the direct control pins have no effect. When this ECE B3 I signal is deasserted (logic-high), the SPI interface is disabled, all SPI registers are reset to their default values, and all available settings are controlled through the control pins. Full-Scale input Range select. In Non-ECM, when this input is set to logic-low or logic-high, the full- scale differential input range for both I- and Q- channel inputs is set to the lower or higher FSR value, respectively. In the ECM, this input is FSR Y3 I ignored and the full-scale range of the I- and Q- channel inputs is independently determined by the setting of Addr: 3h and Addr: Bh, respectively. The high (lower) FSR value in Non-ECM corresponds to the mid (min) available selection in ECM; the FSR range in ECM is greater. Not Connected. This pin is not bonded and may be NC C7 — NONE left floating or connected to any potential. Non-Demuxed Mode select. Setting this input to logic-high causes the digital output bus to be in the 1:1 Non-Demuxed Mode. Setting this input to logic- NDM A5 I low causes the digital output bus to be in the 1:2 Demuxed Mode. This feature is pin-controlled only and remains active during ECM and Non-ECM. Power-down I- and Q-channel. Setting either input to logic-high powers down the respective I- or Q- channel. Setting either input to logic-low brings the respective I- or Q-channel to an operational state PDI U3 after a finite time delay. This pin is active in both I PDQ V3 ECM and Non-ECM. In ECM, each Pin is logically OR'd with its respective Bit. Therefore, either this pin or the PDI and PDQ Bit in the Control Register can be used to power-down the I- and Q-channel (Addr: 0h, Bit 11 and Bit 10), respectively. Serial Clock. In ECM, serial data is shifted into and out of the device synchronously to this clock signal. SCLK C5 I This clock may be disabled and held logic-low, as long as timing specifications are not violated when the clock is enabled or disabled. 8 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ADC12D1000 ADC12D1600 |
Số phần tương tự - ADC12D1000_15 |
|
Mô tả tương tự - ADC12D1000_15 |
|
|
Link URL |
Chính sách bảo mật |
ALLDATASHEET.VN |
Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |