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54ACTQ544F bảng dữ liệu(PDF) 2 Page - National Semiconductor (TI) |
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54ACTQ544F bảng dữ liệu(HTML) 2 Page - National Semiconductor (TI) |
2 / 8 page Connection Diagrams Functional Description The ACTQ544 contains two sets of eight D-type latches, with separate input and output controls for each set. For data flow from A to B, for example, the A-to-B Enable (CEAB) input must be LOW in order to enter data from A 0 –A7 or take data from B 0 –B7, as indicated in the Data I/O Control Table. With CEAB LOW, a LOW signal on the A-to-B Latch Enable (LEAB) input makes the A-to-B latches transparent; a subse- quent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the TRI-STATE B output buffers are active and reflect the data present at the output of the A latches. Control of data flow from B to A is similar, but using the CEBA, LEBA and OEBA inputs. Data I/O Control Table Inputs Latch Output CEAB LEAB OEAB Status Buffers H X X Latched High Z X H X Latched — L L X Transparent — X X H — High Z L X L — Driving H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial A-to-B data flow shown; B-to-A flow control is the same, except using CEBA, LEBA and OEBA Pin Assignment for DIP and Flatpak DS100248-2 Pin Assignment for LCC DS100248-3 www.national.com 2 |
Số phần tương tự - 54ACTQ544F |
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Mô tả tương tự - 54ACTQ544F |
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