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ADS8568SPMR bảng dữ liệu(PDF) 6 Page - Texas Instruments

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ADS8528, ADS8548, ADS8568
SBAS543C – AUGUST 2011 – REVISED FEBRUARY 2016
www.ti.com
Product Folder Links: ADS8528 ADS8548 ADS8568
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
(1)
AI = analog input; AIO = analog input/output; DI = digital input; DIO = digital input/output; DO = digital output; and P = power supply.
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
PARALLEL INTERFACE (PAR/SER = 0)
SERIAL INTERFACE (PAR/SER = 1)
AGND
5, 15, 44,
51, 58, 62
P
Analog ground; connect to the analog ground plane.
ASLEEP
36
DI
Auto-sleep enable input.
When low, the device operates in normal mode.
When high, the device functions in auto-sleep mode where the hold mode and the actual conversion is activated
six conversion clock (tCCLK) cycles after issuing a conversion start using a CONVST_x. This mode is
recommended to save power if the device runs at a lower data rate; see the Reset and Power-Down Modes
section for more details.
AVDD
4, 14, 45,
52, 57, 61
P
Analog power supply.
Decouple according to the Power Supply Recommendations section.
BUSY/INT
35
DO
When CONFIG bit C27 = 0 (BUSY/INT), this pin is a converter busy status output.
This pin transitions high when a conversion is started and transitions low for a single conversion clock cycle
(tCCLK) whenever a channel pair conversion is completed and stays low when the conversion of the last channel
pair completes.
When bit C27 = 1 (BUSY/INT in CONFIG), this pin is an interrupt output. This pin transitions high after a
conversion completes and remains high until the next read access. This mode can only be used if all eight
channels are sampled simultaneously (all CONVST_x tied together). The polarity of the BUSY/INT output can be
changed using the C26 bit (BUSY L/H) in the Configuration register.
CH_A0
42
AI
Analog input of channel A0; channel A is the master channel pair that is always active.
The input voltage range is controlled by the RANGE pin in hardware mode or by Configuration register (CONFIG)
bit C24 (RANGE_A) in software mode. In cases where channel pairs of the device are used at different data
rates, channel pair A must always run at the highest data rate.
CH_A1
47
AI
Analog input of channel A1; channel A is the master channel pair that is always active.
The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C24 (RANGE_A) in
software mode. In cases where channel pairs of the device are used at different data rates, channel pair A must
always run at the highest data rate.
CH_B0
49
AI
Analog input of channel B0. The input voltage range is controlled by the RANGE pin in hardware mode or by
CONFIG bit C23 (RANGE_B) in software mode.
CH_B1
54
AI
Analog input of channel B1. The input voltage range is controlled by the RANGE pin in hardware mode or by
CONFIG bit C23 (RANGE_B) in software mode.
CH_C0
64
AI
Analog input of channel C0. The input voltage range is controlled by the RANGE pin in hardware mode or by
CONFIG bit C21 (RANGE_C) in software mode.
CH_C1
59
AI
Analog input of channel C1. The input voltage range is controlled by the RANGE pin in hardware mode or by
CONFIG bit C21 (RANGE_C) in software mode.
CH_D0
7
AI
Analog input of channel D0.The input voltage range is controlled by the RANGE pin in hardware mode or by
CONFIG bit C19 (RANGE_D) in software mode. This pin can be powered down using CONFIG bit C18 (PD_D) in
software mode.
CH_D1
2
AI
Analog input of channel D1.The input voltage range is controlled by the RANGE pin in hardware mode or by
CONFIG bit C19 (RANGE_D) in software mode. This pin can be powered down using CONFIG bit C18 (PD_D) in
software mode.
CONVST_A
37
DI
Conversion start of channel pair A.
The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_A[1:0].
This signal resets the internal channel state machine that causes the data output to start with conversion results
of channel A0 with the next read access.
CONVST_B
38
DI
Conversion start of channel pair B.
The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_B[1:0].
CONVST_C
39
DI
Conversion start of channel pair C.
The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_C[1:0].
CONVST_D
40
DI
Conversion start of channel pair D.
The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_D[1:0].
CS/FS
13
DI, DI
Chip-select input.
When low, the parallel interface is enabled.
When high, the interface is disabled.
Frame synchronization.
The FS falling edge controls the frame transfer.
DB0/DCIN_D
33
DIO, DI
Data bit 0 (LSB) input/output
When DCEN = 1 and SEL_CD = 1, this pin is the daisy-chain data
input for SDO_D of the previous device in the chain.
When DCEN = 0, connect to DGND.
DB1/DCIN_C
32
DIO, DI
Data bit 1 input/output
When DCEN = 1 and SEL_CD = 1, this pin is the daisy-chain data
input for SDO_C of the previous device in the chain.
When DCEN = 0, connect to DGND.
DB2/DCIN_B
31
DIO, DI
Data bit 2 input/output
When DCEN = 1 and SEL_B = 1, this pin is the daisy-chain data
input for SDO_B of the previous device in the chain.
When DCEN = 0, connect to DGND.
DB3/DCIN_A
30
DIO, DI
Data bit 3 input/output
When DCEN = 1, this pin is the daisy-chain data input for SDO_A
of the previous device in the chain. When DCEN = 0, connect to
DGND.


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