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ADS4142IRGZT bảng dữ liệu(PDF) 5 Page - Texas Instruments

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tên linh kiện ADS4142IRGZT
Giải thích chi tiết về linh kiện  Ultra Low-Power ADC
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ADS4142IRGZT bảng dữ liệu(HTML) 5 Page - Texas Instruments

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36
35
34
33
32
31
30
29
28
27
26
25
12
11
10
9
8
7
6
5
4
3
2
1
DRGND
DRVDD
D1
D0
NC
NC
RESET
SCLK
SDATA
SEN
AVDD
AGND
DRGND
DRVDD
OVR_SDOUT
UNUSED
CLKOUT
DFS
OE
AVDD
AGND
CLKP
CLKM
AGND
Thermal Pad
36
35
34
33
32
31
30
29
28
27
26
25
12
11
10
9
8
7
6
5
4
3
2
1
DRGND
DRVDD
NC
NC
NC
NC
RESET
SCLK
SDATA
SEN
AVDD
AGND
DRGND
DRVDD
OVR_SDOUT
UNUSED
CLKOUT
DFS
OE
AVDD
AGND
CLKP
CLKM
AGND
Thermal Pad
5
ADS4122, ADS4125, ADS4142, ADS4145
www.ti.com
SBAS520B – FEBRUARY 2011 – REVISED JANUARY 2016
Product Folder Links: ADS4122 ADS4125 ADS4142 ADS4145
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Pin Functions - LVDS Mode (continued)
PIN
I/O
DESCRIPTION
NAME
ADS412x
ADS414x
NC
21, 31, 32, 33, 34
21, 31, 32
Do not connect
OE
7
7
I
Output buffer enable input, active high; this pin has an internal 180-k
Ω pull-up resistor to DRVDD.
OVR_SDOUT
3
3
O
This pin functions as an out-of-range indicator after reset, when register bit
READOUT = 0, and functions as a serial register readout pin when READOUT = 1.
RESERVED
23
23
I
Digital control pin, reserved for future use
RESET
30
30
I
Serial interface RESET input.
When using the serial interface mode, the internal registers must initialize through hardware
RESET by applying a high pulse on this pin or by using the software reset option; refer to the
Serial Interface section.
When RESET is tied high, the internal registers are reset to the default values. In this condition,
SEN can be used as an analog control pin.
RESET has an internal 180-k
Ω pull-down resistor.
SCLK
29
29
I
This pin functions as a serial interface clock input when RESET is low. When RESET is high,
SCLK has no function and should be tied to ground. This pin has an internal 180-k
Ω pull-down
resistor.
SDATA
28
28
I
This pin functions as a serial interface data input when RESET is low. When RESET is high,
SDATA functions as a STANDBY control pin (see Table 6). This pin has an internal 180-k
Ω pull-
down resistor.
SEN
27
27
I
This pin functions as a serial interface enable input when RESET is low. When RESET is high,
SEN has no function and should be tied to AVDD. This pin has an internal 180-k
Ω pull-up resistor
to AVDD.
VCM
13
13
O
Outputs the common-mode voltage (0.95 V) that can be used externally to bias the analog input
pins.
ADS412x RGZ Package
48-PIN VQFN With Exposed Thermal Pad
CMOS Mode - Top View
ADS414x RGZ Package
48-PIN VQFN With Exposed Thermal Pad
CMOS Mode -Top View
The thermal pad is connected to DRGND.
Pin Functions - CMOS Mode
PIN
I/O
DESCRIPTION
NAME
ADS412x
ADS414x
AVDD
8, 18, 20, 22, 24, 26
8, 18, 20, 22, 24, 26
I
1.8-V analog power supply
AGND
9, 12, 14, 17, 19, 25
9, 12, 14, 17, 19, 25
I
Analog ground
CLKM
11
11
I
Differential clock input, complement
CLKP
10
10
I
Differential clock input, true
CLKOUT
5
5
O
CMOS output clock
D0
37
33
O
12-bit/14-bit CMOS output data
D1
38
34
O
12-bit/14-bit CMOS output data
D2
39
37
O
12-bit/14-bit CMOS output data


Số phần tương tự - ADS4142IRGZT

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[Old version datasheet]   14-/12-Bit, 65/125MSPS, Ultralow-Power ADC
MARCH2011
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