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ADS4128IRGZ25 bảng dữ liệu(PDF) 4 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  12-Bit, 200-MSPS, Ultralow-Power ADC
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ADS4128IRGZ25 bảng dữ liệu(HTML) 4 Page - Texas Instruments

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29
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26
25
12
11
10
9
8
7
6
5
4
3
2
1
DRGND
DRVDD
NC
NC
NC
NC
RESET
SCLK
SDATA
SEN
AVDD
AGND
DRGND
DRVDD
OVR_SDOUT
CLKOUTM
CLKOUTP
DFW
OE
AVDD
AGND
CLKP
CLKM
AGND
Thermal Pad
ADS4128
SBAS578A – MAY 2012 – REVISED JANUARY 2016
www.ti.com
6 Pin Configuration and Functions
RGZ Package(1)
48-Pin VQFN With Exposed Thermal Pad
LVDS Mode - Top View
The thermal pad is connected to DRGND.
Pin Functions - LVDS Mode
PIN
I/O
DESCRIPTION
NAME
NO.
AGND
9, 12, 14, 17, 19, 25
I
Analog ground
AVDD
8, 18, 20, 22, 24, 26
I
1.8-V analog power supply
CLKM
11
I
Differential clock input, negative
CLKP
10
I
Differential clock input, positive
CLKOUTM
4
O
Differential output clock, negative
CLKOUTP
5
O
Differential output clock, positive
D0_D1_P
38
O
Differential output data D0 and D1 multiplexed, true
D0_D1_M
37
O
Differential output data D0 and D1 multiplexed, complement
D2_D3_P
40
O
Differential output data D2 and D3 multiplexed, true
D2_D3_M
39
O
Differential output data D2 and D3 multiplexed, complement
D4_D5_P
42
O
Differential output data D4 and D5 multiplexed, true
D4_D5_M
41
O
Differential output data D4 and D5 multiplexed, complement
D6_D7_P
44
O
Differential output data D6 and D7 multiplexed, true
D6_D7_M
43
O
Differential output data D6 and D7 multiplexed, complement
D8_D9_P
46
O
Differential output data D8 and D9 multiplexed, true
D8_D9_M
45
O
Differential output data D8 and D9 multiplexed, complement
D10_D11_P
48
O
Differential output data D10 and D11 multiplexed, true
D10_D11_M
47
O
Differential output data D10 and D11 multiplexed, complement
Data format select input. This pin sets the DATA FORMAT (twos complement or offset binary)
DFS
6
I
and the LVDS and CMOS output interface type. See Table 9 for detailed information.
DRGND
1, 36, PAD
I
Digital and output buffer ground
4
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