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ADS42B49IRGCR bảng dữ liệu(PDF) 8 Page - Texas Instruments |
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ADS42B49IRGCR bảng dữ liệu(HTML) 8 Page - Texas Instruments |
8 / 65 page ADS42B49 SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015 www.ti.com Pin Functions - CMOS Mode (continued) PIN I/O DESCRIPTION NAME NO. INP_B 19 Input Differential analog positive input, channel B Serial interface RESET input. When using the serial interface mode, the internal registers must be initialized through a hardware RESET by applying a high pulse on this pin or by using the software reset option; RESET 12 Input refer to the Serial Interface Configuration section. In parallel interface mode, the RESET pin must be permanently tied high. SDATA and SEN are used as parallel control pins in this mode. This pin has an internal 150-k Ω pull-down resistor. This pin functions as a serial interface clock input when RESET is low. SCLK controls the SCLK 13 Input low-speed mode when RESET is tied high; see Table 6 for detailed information. This pin has an internal 150-k Ω pull-down resistor. SDATA 14 Input Serial interface data input; this pin has an internal 150-k Ω pull-down resistor. This pin functions as a serial interface register readout when the READOUT bit is enabled. SDOUT 64 Output When READOUT = 0, this pin is in high-impedance state. This pin functions as a serial interface enable input when RESET is low. SEN controls the SEN 15 Input output interface and data format selection when RESET is tied high; see Table 7 for detailed information. This pin has an internal 150-k Ω pull-up resistor to AVDD. UNUSED 56 — This pin is not used in the CMOS interface This pin outputs the common-mode voltage (1.9 V) that can be used externally to bias the VCM 23 Output analog input pins 8 Specifications 8.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT AVDD –0.3 2.1 V Supply voltage AVDD_BUF –0.3 3.6 V DRVDD –0.3 2.1 V AGND and DRGND –0.3 0.3 V AVDD to DRVDD –2.4 2.4 V (when AVDD leads DRVDD) Voltage between: DRVDD to AVDD –2.4 2.4 V (when DRVDD leads AVDD) AVDD_BUF to DRVDD and AVDD –3.9 3.9 V Minimum INP, INM –0.3 V (3, AVDD_BUF + 0.3) Voltage applied to CLKP, CLKM(2) –0.3 AVDD + 0.3 V RESET, SCLK, SDATA, SEN, –0.3 3.9 V CTRL1, CTRL2, CTRL3 Operating free-air, TA –40 85 °C Temperature Operating junction, TJ 125 °C Storage, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) When AVDD is turned off, TI recommends switching off the input clock (or ensuring the voltage on CLKP, CLKM is less than |0.3 V|). This configuration prevents the ESD protection diodes at the clock input pins from turning on. 8 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: ADS42B49 |
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