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ADC128S052QCMTX bảng dữ liệu(PDF) 3 Page - Texas Instruments |
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ADC128S052QCMTX bảng dữ liệu(HTML) 3 Page - Texas Instruments |
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3 / 32 page  1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CS SCLK V A DOUT AGND DIN IN0 V D IN1 DGND IN2 IN7 IN3 IN6 IN4 IN5 ADC128S052 ADC128S052, ADC128S052-Q1 www.ti.com SNAS333E – AUGUST 2005 – REVISED DECEMBER 2015 5 Pin Configuration and Functions PW Package 16-Pin TSSOP Top View Pin Functions PIN TYPE DESCRIPTION NO. NAME Chip select. On the falling edge of CS, a conversion process begins. Conversions continue 1 CS Digital I/O as long as CS is held low. Positive analog supply pin. This voltage is also used as the reference voltage. This pin must Power 2 VA be connected to a quiet 2.7-V to 5.25-V source and bypassed to GND with 1-µF and 0.1-µF Supply monolithic ceramic capacitors located within 1 cm of the power pin. Power 3 AGND The ground return for the analog supply and signals. Supply 4 5 6 7 IN0 to IN7 Analog I/O Analog inputs. These signals can range from 0 V to VREF. 8 9 10 11 Power 12 DGND The ground return for the digital supply and signals. Supply Power Positive digital supply pin. This pin must be connected to a 2.7-V to VA supply, and bypassed 13 VD Supply to GND with a 0.1-µF monolithic ceramic capacitor located within 1 cm of the power pin. Digital data input. The control register of the ADC128S052 is loaded through this pin on 14 DIN Digital I/O rising edges of the SCLK pin. Digital data output. The output samples are clocked out of this pin on the falling edges of the 15 DOUT Digital I/O SCLK pin. Digital clock input. The ensured performance range of frequencies for this input is 16 SCLK Digital I/O 3.2 MHz to 8 MHz. This clock directly controls the conversion and readout processes. Copyright © 2005–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: ADC128S052 ADC128S052-Q1 |
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