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ADS42B49IRGC25 bảng dữ liệu(PDF) 6 Page - Texas Instruments

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ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
www.ti.com
Pin Functions - LVDS Mode (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
DA10P, DA10M
53, 52
Output
Channel A differential output data D10 and D11 multiplexed
DA12P, DA12M
55, 54
Output
Channel A differential output data D12 and D13 multiplexed
DB0P, DB0M
61, 60
Output
Channel B differential output data pair, D0 and D1 multiplexed
DB2P, DB2M
63, 62
Output
Channel B differential output data D2 and D3 multiplexed
DB4P, DB4M
3, 2
Output
Channel B differential output data D4 and D5 multiplexed
DB6P, DB6M
5, 4
Output
Channel B differential output data D6 and D7 multiplexed
DB8P, DB8M
7, 6
Output
Channel B differential output data D8 and D9 multiplexed
DB10P, DB10M
9, 8
Output
Channel B differential output data D10 and D11 multiplexed
DB12P, DB12M
11, 10
Output
Channel B differential output data D12 and D13 multiplexed
DRGND
39, 49, 59, PAD
Input
Output buffer ground, should be shorted on-board to analog ground.
DRVDD
1, 38, 48, 58
Input
Output buffer supply
INM_A
30
Input
Differential analog negative input, channel A
INP_A
29
Input
Differential analog positive input, channel A
INM_B
20
Input
Differential analog negative input, channel B
INP_B
19
Input
Differential analog positive input, channel B
Serial interface RESET input.
When using the serial interface mode, the internal registers must be initialized through a
hardware RESET by applying a high pulse on this pin or by using the software reset
RESET
12
Input
option; refer to the Serial Interface Configuration section.
In parallel interface mode, the RESET pin must be permanently tied high. SCLK and SEN
are used as parallel control pins in this mode. This pin has an internal 150-k
Ω pull-down
resistor.
This pin functions as a serial interface clock input when RESET is low. SCLK controls the
SCLK
13
Input
low-speed mode selection when RESET is tied high; see Table 6 for detailed information.
This pin has an internal 150-k
Ω pull-down resistor.
SDATA
14
Input
Serial interface data input; this pin has an internal 150-k
Ω pull-down resistor.
This pin functions as a serial interface register readout when the READOUT bit is enabled.
SDOUT
64
Output
When READOUT = 0, this pin is in high-impedance state.
This pin functions as a serial interface enable input when RESET is low. SEN controls the
SEN
15
Input
output interface and data format selection when RESET is tied high; see Table 7 for
detailed information. This pin has an internal 150-k
Ω pull-up resistor to AVDD.
This pin outputs the common-mode voltage (1.9 V) that can be used externally to bias the
VCM
23
Output
analog input pins
6
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