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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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CAP1126 bảng dữ liệu(PDF) 10 Page - Microchip Technology |
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CAP1126 bảng dữ liệu(HTML) 10 Page - Microchip Technology |
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10 / 73 page  CAP1126 DS00001623B-page 10 2015 Microchip Technology Inc. Note 3-5 The ALERT pin will not glitch high or low at power up if connected to VDD or another voltage. Note 3-6 The SMCLK and SMDATA pins will not glitch low at power up if connected to VDD or another voltage. Input High Voltage VIH 2.0 V Input Low Voltage VIL 0.8 V Leakage Current ILEAK ±5 uA powered or unpowered TA < 85°C pull-up voltage < 3.6V if unpowered RESET Pin Release to conversion ready tRESET 170 200 ms SMBus Timing Input Capacitance CIN 5pF Clock Frequency fSMB 10 400 kHz Spike Suppression tSP 50 ns Bus Free Time Stop to Start tBUF 1.3 us Start Setup Time tSU:STA 0.6 us Start Hold Time tHD:STA 0.6 us Stop Setup Time tSU:STO 0.6 us Data Hold Time tHD:DAT 0 us When transmitting to the master Data Hold Time tHD:DAT 0.3 us When receiving from the master Data Setup Time tSU:DAT 0.6 us Clock Low Period tLOW 1.3 us Clock High Period tHIGH 0.6 us Clock / Data Fall Time tFALL 300 ns Min = 20+0.1CLOAD ns Clock / Data Rise Time tRISE 300 ns Min = 20+0.1CLOAD ns Capacitive Load CLOAD 400 pF per bus line SPI Timing Clock Period tP 250 ns Clock Low Period tLOW 0.4 x tP 0.6 x tP ns Clock High Period tHIGH 0.4 x tP 0.6 x tP ns Clock Rise / Fall time tRISE / tFALL 0.1 x tP ns Data Output Delay tD:CLK 10 ns Data Setup Time tSU:DAT 20 ns Data Hold Time tHD:DAT 20 ns SPI_CS# to SPI_CLK setup time tSU:CS 0ns Wake Time tWAKE 10 20 us SPI_CS# asserted to CLK assert TABLE 3-2: ELECTRICAL SPECIFICATIONS (CONTINUED) VDD = 3V to 3.6V, TA = 0°C to 85°C, all typical values at TA = 27°C unless otherwise noted. Characteristic Symbol Min Typ Max Unit Conditions |
Số phần tương tự - CAP1126 |
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Mô tả tương tự - CAP1126 |
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