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TSA7887ARZ bảng dữ liệu(PDF) 5 Page - Silicon Laboratories

tên linh kiện TSA7887ARZ
Giải thích chi tiết về linh kiện  A Micropower, 2-channel, 125-ksps, Serial-Output 12-bit SAR ADC
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nhà sản xuất  SILABS [Silicon Laboratories]
Trang chủ  http://www.silabs.com
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TSA7887
TSA7887 Rev. 1.0
Page 5
TIMING SPECIFICATIONS1
Parameter
Limit at TMIN, TMAX
Unit
Description
(A, B Versions)
4.75V to 5.25V
2.7V to 3.6V
fSCLK
2
2
2
MHz (max)
tCONVERT
14.5 × tSCLK
14.5 × tSCLK
tACQ
1.5 × tSCLK
1.5 × tSCLK
Throughput time = tCONVERT + tACQ = 16 tSCLK
t1
10
10
ns (min)
CS to SCLK setup time
t2
3
30
60
ns (max)
Delay from CS until DOUT three-state disabled
t3
3
75
100
ns (max)
Data access time after SCLK falling edge
t4
20
20
ns (min)
Data setup time prior to SCLK rising edge
t5
20
20
ns (min)
Data valid to SCLK hold time
t6
0.4 × tSCLK
0.4 × tSCLK
ns (min)
SCLK high pulse width
t7
0.4 × tSCLK
0.4 × tSCLK
ns (min)
SCLK low pulse width
t8
4
80
80
ns (max)
CS rising edge to DOUT high-Z
t9
5
5
μs (typ)
Power-up time from shutdown
Note 1: Timing specifications are sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of
VDD) and timed relative to a voltage level of 1.6V.
Note 2: The mark/space ratio for the SCLK input is 40/60 to 60/40. See Serial Interface section for additional details.
Note 3: Measured with the load circuit as shown below and defined as the time required for the output to cross 0.8V or 2.0V.
Note 4: Timing specification t8 is derived from the measured time taken by the data outputs to change 0.5V when loaded with the circuit shown
below. The measured result is then extrapolated back to remove the effects of charging or discharging the 50pF capacitor. This
means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the TSA7887 and is independent of bus
loading.
Load Circuit Used for TSA7887’s Digital Output Timing
Specifications.


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