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TS12012ITD1022T bảng dữ liệu(PDF) 4 Page - Silicon Laboratories

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TS12011/TS12012
Page 4
TS12011/12 Rev. 1.0
VDD = 0.8V, VSS = 0V, VCOMPIN+/- = 0V, VAMPIN+/- = 0V, VAMPOUT = (VDD + VSS)/2, VCOMPOUT = HiZ. TA = -40°C to +85°C, unless otherwise noted.
Typical values are at TA = +25°C. See note 1.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CONTROL PIN SECTION
LHDET Input Low Voltage
VIL
Comparator Latched Output
Enabled
0.8V
≤ V
DD ≤ 1.1V
0.1
V
1.1V < VDD ≤ 2.5V
0.2
LHDET Input High Voltage
VIH
Comparator Latched Output
Disabled
0.8V
≤ V
DD ≤ 1.1V
VDD - 0.1
V
1.1V < VDD ≤ 2.5V
1
LHDET Input Leakage
VLHDET = VSS; VLHDET = 5.5V
100
nA
Note 1: All devices are 100% production tested at TA = +25°C and are guaranteed by characterization for TA = TMIN to TMAX, as specified.
Note 2: VOS is defined as the center of the hysteresis band at the input minus VIN(CM).
Note 3: The hysteresis-related trip points are defined by the edges of the hysteresis band and measured with respect to the center of
the hysteresis band.
Note 4: The propagation delays are specified with an output load capacitance of CL = 15pF. VOVERDRIVE is defined above and is beyond the
offset voltage and hysteresis of the comparator input.


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