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ADF5904WCCPZ-RL7 bảng dữ liệu(PDF) 9 Page - Analog Devices

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Data Sheet
ADF5904
THEORY OF OPERATION
RF PATH
The ADF5904 contains four identical 24 GHz downconverter
channels. Each channel contains a balun that converts the
single-ended input into a differential signal for the rest of the
downconverter path (see Figure 15). This balun is followed by
a LNA that feeds the downconverter mixer.
AVDD
2kΩ
2kΩ
RXx_RF
GND
GND
AVDD
AVDD
BALUN
Figure 15. RF Input Stage
LO PATH
The four downconverter channels share the same LO path. The
LO path contains a balun that converts the single-ended input
to a differential signal to drive the mixer (see Figure 16).
AVDD
400Ω
400Ω
20Ω
20Ω
LO_IN
GND
GND
AVDD
AVDD
BALUN
Figure 16. LO Input Stage
INPUT SHIFT REGISTER
The ADF5904 digital section includes power-down bits and test
modes to read back registers. Data is clocked into the 32-bit
input shift register on each rising edge of CLK. The data is
clocked in MSB first. Data is transferred from the input shift
register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2 and C1) in the input shift register. These are the two
LSBs (DB1 and DB0, respectively), as shown in Table 5. The
truth table for these bits is shown in Table 5. Figure 18 to Figure 20
show a summary of how the latches are programmed.
PROGRAM MODES
Table 5 and Figure 18 through Figure 20 show how to set up the
program modes in the ADF5904.
Table 5. C1 and C2 Truth Table
Control Bits
C2 (DB1)
C1 (DB0)
Register
0
0
R0
0
1
R1
1
0
R2
1
1
R3
Rev. 0 | Page 9 of 15


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ADF5904WCCPZ-RL7 AD-ADF5904WCCPZ-RL7 Datasheet
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   4-Channel, 24 GHz, Receiver Downconverter
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