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LMX2430TMX bảng dữ liệu(PDF) 7 Page - Texas Instruments |
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LMX2430TMX bảng dữ liệu(HTML) 7 Page - Texas Instruments |
7 / 53 page LMX2430, LMX2433, LMX2434 www.ti.com SNAS187D – FEBRUARY 2003 – REVISED JANUARY 2016 Electrical Characteristics (continued) VCC = EN = 2.5 V, −40°C ≤ TA ≤ +85°C, unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PHASE NOISE CHARACTERISTICS TCXO Reference Source RF synthesizer normalized phase noise dBc/ LNRF(f) RF_CPG Bit = 1 –219 contribution(6) Hz IF_PD Bit = 1 TCXO Reference Source IF synthesizer normalized phase noise dBc/ LNIF(f) IF_CPG Bit = 1 –214 contribution(6) Hz RF_PD Bit = 1 fFinRF = 2750 MHz f = 10-kHz offset fCOMPRF = 1 MHz Loop Bandwidth = 100 kHz NRF = 2750 dBc/ LMX2430 –90.3 fOSCin = 10 MHz Hz vOSCin = 1 VPP RF_CPG Bit = 1 IF_PD Bit = 1 TA = 25 oC(7) fFinRF = 3200 MHz f = 10-kHz offset fCOMPRF = 1 MHz Loop Bandwidth = 100 kHz RF synthesizer single- NRF = 3200 dBc/ LRF(f) side band phase noise LMX2433 –88.9 fOSCin = 10 MHz Hz measured vOSCin = 1 VPP RF_CPG Bit = 1 IF_PD Bit = 1 TA = 25°C (7) fFinRF = 4700 MHz f = 10-kHz offset fCOMPRF = 1 MHz Loop Bandwidth = 100 kHz NRF = 4700 dBc/ LMX2434 –85.6 fOSCin = 10 MHz Hz vOSCin = 1 VPP RF_CPG Bit = 1 IF_PD Bit = 1 TA = 25°C (7) (6) Normalized Phase Noise Contribution is defined as LN(f) = L(f) − 20 log (N) − 10 log (fCOMP), where L(f) is defined as the single side band phase noise measured at an offset frequency, f, in a 1-Hz bandwidth. The offset frequency, f, must be chosen sufficiently smaller than the loop bandwidth of the PLL, yet large enough to avoid substantial phase noise contribution from the reference source. N is the value selected for the feedback divider and fCOMP is the RF/IF phase and frequency detector comparison frequency. (7) The synthesizer phase noise is measured with the LMX2430PW/LMX2430NPE evaluation boards and the HP8566B Spectrum Analyzer. 7.5 Timing Requirements See (1) MIN NOM MAX UNIT MICROWIRE INTERFACE tCS DATA to CLK set-up time 50 ns tCH DATA to CLK hold time 10 ns tCWH CLK pulse width HIGH 50 ns tCWL CLK pulse width LOW 50 ns tES CLK to LE set-up time 50 ns tEW LE pulse width 50 ns (1) Refer to LMX243x Serial Data Input Timing figure. Copyright © 2003–2016, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LMX2430 LMX2433 LMX2434 |
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